本軟件是關(guān)于MAX338, MAX339的英文數(shù)據(jù)手冊(cè)：MAX338, MAX339 8通道/雙4通道、低泄漏、CMOS模擬多路復(fù)用器 The MAX338/MAX339 are monolithic, CMOS analog multiplexers (muxes). The 8-channel MAX338 is designed to connect one of eight inputs to a common output by control of a 3-bit binary address. The dual, 4-channel MAX339 is designed to connect one of four inputs to a common output by control of a 2-bit binary address. Both devices can be used as either a mux or a demux. On-resistance is 400Ω max, and the devices conduct current equally well in both directions. These muxes feature extremely low off leakages (less than 20pA at +25°C), and extremely low on-channel leakages (less than 50pA at +25°C). The new design offers guaranteed low charge injection (1.5pC typ) and electrostatic discharge (ESD) protection greater than 2000V, per method 3015.7. These improved muxes are pin-compatible upgrades for the industry-standard DG508A and DG509A. For similar Maxim devices with lower leakage and charge injection but higher on-resistance, see the MAX328 and MAX329.
上傳時(shí)間： 2013-11-12
上傳用戶：18711024007
This book evolved over the past ten years from a set of lecture notes developed while teaching the undergraduate Algorithms course at Berkeley and U.C. San Diego. Our way of teaching this course evolved tremendously over these years in a number of directions, partly to address our students' background (undeveloped formal skills outside of programming), and partly to reect the maturing of the eld in general, as we have come to see it. The notes increasingly crystallized into a narrative, and we progressively structured the course to emphasize the ?story line? implicit in the progression of the material. As a result, the topics were carefully selected and clustered. No attempt was made to be encyclopedic, and this freed us to include topics traditionally de-emphasized or omitted from most Algorithms books.
標(biāo)簽： Algorithms 算法
上傳時(shí)間： 2013-11-11
上傳用戶：JamesB
MOTION BUILDER Ver.2 是用于監(jiān)控 KV-H20/H20S/H40S/H20G 的參數(shù)設(shè)定以及當(dāng)前動(dòng)作狀態(tài)的軟件。 在 PC 上可以設(shè)定復(fù)雜的參數(shù)，并可以在顯示畫面上監(jiān)控正在運(yùn)行的 KV-H20/H20S/H40S/H20G。 關(guān)于 MOTION BUILDER Ver.2 概要、功能與使用方法的詳細(xì)說明。在安裝之前，請(qǐng)仔細(xì)閱讀本手冊(cè)，并充分 理解。 注意 1、使用 MOTION BUILDER Ver.2 時(shí)，必須在可以使用 KV-H20/H20S/H40S/H20G 上 連接的緊急停止開關(guān)的地方使用。 通訊異常時(shí)，不接受 MOTION BUILDER Ver.2 的“強(qiáng)制停止”，可能會(huì)導(dǎo)致事故指示發(fā)生。發(fā)生通信異常時(shí)，MOTION BUILDER Ver.2 的“強(qiáng)制停止”按鈕將不起作用。 2、JOG 過程中，不能采用斷開 PLC 的連接電纜等手段停止通訊。 KV-H20/H20S/H40S/H20G 單元的 JOG 繼電器會(huì)一直保持 ON，機(jī)器繼續(xù)運(yùn)轉(zhuǎn)，并可能導(dǎo)致事故發(fā)生。 3、執(zhí)行監(jiān)控或者寫入?yún)?shù)（設(shè)定）時(shí)，不能斷開和 PLC 的連接電纜。 否則會(huì)發(fā)生通訊錯(cuò)誤，PC 可能會(huì)被重啟。KV-H20/H20S/H40S/H20G 內(nèi)的數(shù)據(jù)可 能會(huì)損壞。 4、在 RUN 過程中，KV-1000/700 進(jìn)行 JOG 示教時(shí)，必須在 PROG 模式下實(shí)施。 如果掃描時(shí)間較長，則反映的時(shí)間變長，且可能發(fā)生無法預(yù)料的動(dòng)作。 5、發(fā)送到 KV-1000/700 的單元設(shè)定信息必須與當(dāng)前打開的梯形圖程序的單元設(shè)定信 息一致。如果設(shè)定信息不同，則顯示錯(cuò)誤，且不運(yùn)行。 6、錯(cuò)誤操作或者靜電等會(huì)引起數(shù)據(jù)變化或者去失，為了保護(hù)數(shù)據(jù)，請(qǐng)定期進(jìn)行備份。 指示 關(guān)于數(shù)據(jù)的變化或者消失引起的損失，本公司不負(fù)任何責(zé)任，請(qǐng)諒解。 7、保存數(shù)據(jù)時(shí)，如果需要保留原來保存的數(shù)據(jù)，則選擇“重命名保存”。 如果“覆蓋保存”則會(huì)失去原來保存的數(shù)據(jù)。 運(yùn)行環(huán)境及系統(tǒng)配置 運(yùn)行 MOTION BUILDER Ver.2 ，必須具備如下環(huán)境。 請(qǐng)確認(rèn)您使用的系統(tǒng)是否符合如下條件、是否備齊了必需的設(shè)備。 對(duì)應(yīng)的 PC 機(jī)型 • IBM PC 以及 PC/AT 兼容機(jī)（DOS/V） 系統(tǒng)配置 • CPU Pentium 133 MHz 以上 支持 Windows 的打印 （推薦 Pentium 200 MHz 以上） • 內(nèi)存容量擴(kuò)展內(nèi)存 64MB 以上 • 硬盤可用空間 20MB 以上 • CD-ROM 驅(qū)動(dòng)器 • 接口 RS-232C 或者 USB
標(biāo)簽： BUILDER MOTION Ver 使用說明書
上傳時(shí)間： 2013-10-08
上傳用戶：fujiura
This example shows how to update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI). The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDGISR the counter is refreshed to prevent a WWDG reset and led connected to PC.07is toggled.The EXTI line9 is connected to PB.09 pin and configured to generate an interrupton falling edge.In the NVIC, EXTI line9 to 5 interrupt vector is enabled with priority equal to 0and the WWDG interrupt vector is enabled with priority equal to 1 (EXTI IT > WWDG IT). The EXTI Line9 will be used to simulate a software failure: once the EXTI line9event occurs (by pressing Key push-button on EVAL board) the correspondent interruptis served, in the ISR the led connected to PC.07 is turned off and the EXTI line9pending bit is not cleared. So the CPU will execute indefinitely EXTI line9 ISR andthe WWDG ISR will never be entered(WWDG counter not updated). As result, when theWWDG counter falls to 3Fh the WWDG reset occurs.If the EXTI line9 event don抰 occurs the WWDG counter is indefinitely refreshed inthe WWDG ISR which prevent from WWDG reset. If the WWDG reset is generated, after resuming from reset a led connected to PC.06is turned on. In this example the system is clocked by the HSE(8MHz).
上傳時(shí)間： 2013-11-11
上傳用戶：gundamwzc
C++在幾乎所有的計(jì)算環(huán)境中都非常普及，而且可以用于幾乎所有的應(yīng)用程序。C++從C中繼承了過程化編程的高效性，并集成了面向?qū)ο缶幊痰墓δ?。C++在其標(biāo)準(zhǔn)庫中提供了大量的功能。有許多商業(yè)C++庫支持?jǐn)?shù)量眾多的操作系統(tǒng)環(huán)境和專業(yè)應(yīng)用程序。但因?yàn)樗膬?nèi)容太多了，所以掌握C++并不十分容易。本書詳述了C++語言的各個(gè)方面，包括數(shù)據(jù)類型、程序控制、函數(shù)、指針、調(diào)試、類、重載、繼承、多態(tài)性、模板、異常和輸入輸出等內(nèi)容。每一章都以前述內(nèi)容為基礎(chǔ)，每個(gè)關(guān)鍵點(diǎn)都用具體的示例進(jìn)行詳細(xì)的講解。本書基本不需要讀者具備任何C++知識(shí)，書中包含了理解C++的所有必要知識(shí)，讀者可以從頭開始編寫自己的C++程序。本書也適合于具備另一種語言編程經(jīng)驗(yàn)但希望全面掌握C++語言的讀者。 I created all the files under Microsoft Windows so lines are terminated by CR/LF. In addition to this "ReadMe" file you will find three zip archives in the primary archive, so you need to unzip each of these to get at the code. 為PDG格式,這有pdg閱讀器下載|pdg文件閱讀器下載
標(biāo)簽： 源代碼
上傳時(shí)間： 2013-11-18
上傳用戶：gaoqinwu
There has long been a need for portable ultrasoundsystems that have good resolution at affordable costpoints. Portable systems enable healthcare providersto use ultrasound in remote locations such asdisaster zones, developing regions, and battlefields,where it was not previously practical to do so.
標(biāo)簽： Xilinx 便攜式 超聲系統(tǒng) 器件
上傳時(shí)間： 2015-01-01
上傳用戶：hfnishi
Nios II軟件構(gòu)建工具入門 The Nios® II Software Build Tools (SBT) allows you to construct a wide variety of complex embedded software systems using a command-line interface. From this interface, you can execute Software Built Tools command utilities, and use scripts other tools) to combine the command utilities in many useful ways. This chapter introduces you to project creation with the SBT at the command line This chapter includes the following sections: ■ “Advantages of Command-Line Software Development” ■ “Outline of the Nios II SBT Command-Line Interface” ■ “Getting Started in the SBT Command Line” ■ “Software Build Tools Scripting Basics” on page 3–8
上傳時(shí)間： 2013-11-15
上傳用戶：nanxia
Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
上傳時(shí)間： 2013-11-21
上傳用戶：不懂夜的黑
Design techniques for electronic systems areconstantly changing. In industries at the heart of thedigital revolution, this change is especially acute.Functional integration, dramatic increases incomplexity, new standards and protocols, costconstraints, and increased time-to-market pressureshave bolstered both the design challenges and theopportunities to develop modern electronic systems.One trend driving these changes is the increasedintegration of core logic with previously discretefunctions to achieve higher performance and morecompact board designs.
標(biāo)簽： System Xilinx FPGA 151
上傳時(shí)間： 2013-11-23
上傳用戶：kangqiaoyibie
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
標(biāo)簽： Virtex FPGA PCB 設(shè)計(jì)手冊(cè)
上傳時(shí)間： 2013-11-11
上傳用戶：zwei41
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