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  • 關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in

    關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.

    標簽: investigates implementing pipelines circuits

    上傳時間: 2015-07-26

    上傳用戶:CHINA526

  • 上下文無關文法(Context-Free Grammar, CFG)是一個4元組G=(V, T, S, P)

    上下文無關文法(Context-Free Grammar, CFG)是一個4元組G=(V, T, S, P),其中,V和T是不相交的有限集,S∈V,P是一組有限的產生式規則集,形如A→α,其中A∈V,且α∈(V∪T)*。V的元素稱為非終結符,T的元素稱為終結符,S是一個特殊的非終結符,稱為文法開始符。 設G=(V, T, S, P)是一個CFG,則G產生的語言是所有可由G產生的字符串組成的集合,即L(G)={x∈T* | Sx}。一個語言L是上下文無關語言(Context-Free Language, CFL),當且僅當存在一個CFG G,使得L=L(G)。 *⇒ 例如,設文法G:S→AB A→aA|a B→bB|b 則L(G)={a^nb^m | n,m>=1} 其中非終結符都是大寫字母,開始符都是S,終結符都是小寫字母。

    標簽: Context-Free Grammar CFG

    上傳時間: 2013-12-10

    上傳用戶:gaojiao1999

  • 一:需求分析 1. 問題描述 魔王總是使用自己的一種非常精練而抽象的語言講話,沒人能聽懂,但他的語言是可逐步解釋成人能聽懂的語言,因為他的語言是由以下兩種形式的規則由人的語言逐步抽象上去的: -

    一:需求分析 1. 問題描述 魔王總是使用自己的一種非常精練而抽象的語言講話,沒人能聽懂,但他的語言是可逐步解釋成人能聽懂的語言,因為他的語言是由以下兩種形式的規則由人的語言逐步抽象上去的: ----------------------------------------------------------- (1) a---> (B1)(B2)....(Bm) (2)[(op1)(p2)...(pn)]---->[o(pn)][o(p(n-1))].....[o(p1)o] ----------------------------------------------------------- 在這兩種形式中,從左到右均表示解釋.試寫一個魔王語言的解釋系統,把 他的話解釋成人能聽得懂的話. 2. 基本要求: 用下述兩條具體規則和上述規則形式(2)實現.設大寫字母表示魔王語言的詞匯 小寫字母表示人的語言的詞匯 希臘字母表示可以用大寫字母或小寫字母代換的變量.魔王語言可含人的詞匯. (1) B --> tAdA (2) A --> sae 3. 測試數據: B(ehnxgz)B 解釋成 tsaedsaeezegexenehetsaedsae若將小寫字母與漢字建立下表所示的對應關系,則魔王說的話是:"天上一只鵝地上一只鵝鵝追鵝趕鵝下鵝蛋鵝恨鵝天上一只鵝地上一只鵝". | t | d | s | a | e | z | g | x | n | h | | 天 | 地 | 上 | 一只| 鵝 | 追 | 趕 | 下 | 蛋 | 恨 |

    標簽: 語言 抽象

    上傳時間: 2014-12-02

    上傳用戶:jkhjkh1982

  • The programming port of all the FP PLC’s support OPEN MEWTOCOL-COM. This is very useful when you wan

    The programming port of all the FP PLC’s support OPEN MEWTOCOL-COM. This is very useful when you want to monitor PLC values/bits or to set PLC values or bits via your COMPUTER. You can use any language such as Basic, C, Pascal, Assembler or even if other suppliers of PLCs can send ASCII strings, they can talk to our PLCs to exchange data.

    標簽: MEWTOCOL-COM programming support useful

    上傳時間: 2015-12-08

    上傳用戶:youmo81

  • SQL Server Security Distilled, Second Edition by Morris Lewis ISBN:1590592190 Apress © 2004

    SQL Server Security Distilled, Second Edition by Morris Lewis ISBN:1590592190 Apress © 2004 (352 pages) This book takes an in-depth look at what you can do to secure data in SQL Server, shows how to authenticate access to data on the server, and authorizes what users can and can t do with that data, in versions 6.5, 7.0, and 2000.

    標簽: 1590592190 Distilled Security Edition

    上傳時間: 2015-12-25

    上傳用戶:hj_18

  • You imagine? Right, there s more than one possibility, this time I ll give you tree. One for your pr

    You imagine? Right, there s more than one possibility, this time I ll give you tree. One for your private data, one for the common data in order to receive data from other applications like Excel, WinWord etc. and at last, I ll give you a handy-dandy class you can derive ANY MFC object from, to make it a drop target

    標簽: possibility imagine Right there

    上傳時間: 2013-12-21

    上傳用戶:jichenxi0730

  • This folder has some scritps that you may find usefull. All of it comes from questions that I ve r

    This folder has some scritps that you may find usefull. All of it comes from questions that I ve received in my email. If you have a new request/question, feel free to send it to marceloperlin@gmail.com. But please, don t ask me to do your homework. Passing_your_param0 This folder contains instructions (and m files) for passing you own initial parameters to the fitting function. I also included a simple simulation script that will create random initial coefficients (under the proper bounds) and fit the model to the data.

    標簽: that questions scritps usefull

    上傳時間: 2013-12-28

    上傳用戶:netwolf

  • // This Communications Component is implemented using separate Read and Write // threads. Messages

    // This Communications Component is implemented using separate Read and Write // threads. Messages from the threads are posted to the Comm control which is // an invisible window. To handle data from the comm port, simply // attach a handler to OnReceiveData . There is no need to free the memory // buffer passed to this handler. If TAPI is used to open the comm port, some // changes to this component are needed ( StartComm currently opens the comm // port). The OnRequestHangup event is included to assist this. // // David Wann // Stamina Software // 28/02/96 // davidwann@hunterlink.net.au

    標簽: Communications implemented Component Messages

    上傳時間: 2016-05-30

    上傳用戶:zhangyigenius

  • Flash中內置了一個狀態寄存器(Status Register

    Flash中內置了一個狀態寄存器(Status Register,SR)來指示Flash的當前工作狀態和各種操作是否成功。要讀取SR的當前值需要向CUI發送讀狀態寄存器命令(Read Status Register),命令碼為0x70,SR中的內容將在DQ[7:0]上輸出。The Read Status Register (0x70)command causes subsequent reads to output data from the SR until another command is issued. The SR bits are output on DQ[7:0].

    標簽: Register Status Flash 內置

    上傳時間: 2016-08-12

    上傳用戶:thesk123

  • The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general co

    The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control and data transfer communication between ICs. Some of the features of the I2C bus are: • Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A 12V supply line (500mA max.) for powering the peripherals often may be present. • Each device connected to the bus is software addressable by a unique address and simple master/ slave relationships exist at all times masters can operate as master-transmitters or as master-receivers. • The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer systems. • Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard mode or up to 400 KBit/s in the fast mode.

    標簽: bus bidirectional primarily designed

    上傳時間: 2013-12-11

    上傳用戶:jeffery

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