Building a RISC System in an FPGA
標(biāo)簽： Building System RISC FPGA
上傳時(shí)間： 2013-09-04
上傳用戶(hù)：朗朗乾坤
Cadence guide for verilog
標(biāo)簽： Cadence verilog guide for
上傳時(shí)間： 2013-09-04
上傳用戶(hù)：123454
Allegro design guide \r\nAllegro design guide
標(biāo)簽： Allegro design guide
上傳時(shí)間： 2013-09-07
上傳用戶(hù)：mnacyf
Altium Designer Guide by Univ of Nevada
標(biāo)簽： Designer Altium Nevada Guide
上傳時(shí)間： 2013-09-11
上傳用戶(hù)：qingzhuhu
gerber-to-protel is a pdf file ,which is used for convert bmp to pcb.
標(biāo)簽： gerber-to-protel file is
上傳時(shí)間： 2013-09-18
上傳用戶(hù)：liuxinyu2016
protel_lib-PIC16 is a protel lib file.
標(biāo)簽： protel_lib-PIC protel file lib
上傳時(shí)間： 2013-09-18
上傳用戶(hù)：hn891122
Many CAD users dismiss schematic capture as a necessary evil in the process of creating\r\nPCB layout but we have always disputed this point of view. With PCB layout now offering\r\nautomation of both component placement and track routing, getting the des
標(biāo)簽： schematic necessary creating dismiss
上傳時(shí)間： 2013-09-25
上傳用戶(hù)：baiom
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
標(biāo)簽： Modelling Guide Navy VHDL
上傳時(shí)間： 2014-12-23
上傳用戶(hù)：xinhaoshan2016
本文詳細(xì)討論了VHDL語(yǔ)句對(duì)PLD設(shè)計(jì)的影響和設(shè)計(jì)經(jīng)驗(yàn)，經(jīng)典文章，值得仔細(xì)閱讀消化。,PLD Programming Using VHDL
標(biāo)簽： Programming Using VHDL PLD
上傳時(shí)間： 2013-11-17
上傳用戶(hù)：teddysha
Methods for designing a maintenance simulation training system for certain kind of radio are introduced. Fault modeling method is used to establish the fault database. The system sets up some typical failures， follow the prompts trainers can locate the fault source and confirm the type to accomplish corresponding fault maintenance training. A training evaluation means is given to examining and evaluating the training performance. The system intuitively and vividly shows the fault maintenance process， it can not only be used in teaching， but also in daily maintenance training to efficiently improve the maintenance operation level. Graphical programming language LabVIEW is used to develop the system platform.
標(biāo)簽： 電臺(tái)維修 模擬訓(xùn)練 方法研究 系統(tǒng)設(shè)計(jì)
上傳時(shí)間： 2013-11-19
上傳用戶(hù)：3294322651
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