===================================== GoAhead WebServer 2.1.8 Release Notes ===================================== .. NOTES: .. This document is maintained using the reStructuredText markup system. .. You may download this from <http://docutils.sf.net>. Also note that running .. the docutils code requires that a version of Python version 2.1 or later .. be installed on the machine. Since the GoAhead release procedure itself .. runs in Python, this should not be a problem. .. .. To add new entries to the release notes, follow the markup shown below .. (releases should be underlined with a row of '=' characters, each item .. noted within a release should be underlined with '-' characters.
上傳時間： 2016-01-30
上傳用戶：zrxkn
===================================== GoAhead WebServer 2.1.8 Release Notes ===================================== .. NOTES: .. This document is maintained using the reStructuredText markup system. .. You may download this from <http://docutils.sf.net>. Also note that running .. the docutils code requires that a version of Python version 2.1 or later .. be installed on the machine. Since the GoAhead release procedure itself .. runs in Python, this should not be a problem. .. .. To add new entries to the release notes, follow the markup shown below .. (releases should be underlined with a row of '=' characters, each item .. noted within a release should be underlined with '-' characters.
標簽： web html embed server arm small http
上傳時間： 2016-01-30
上傳用戶：zrxkn
FPGA讀寫SD卡讀取BMP圖片通過LCD顯示例程實驗 Verilog邏輯源碼Quartus工程文件+文檔說明,FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 實驗簡介在前面的實驗中我們練習了 SD 卡讀寫，VGA 視頻顯示等例程，本實驗將 SD 卡里的 BMP 圖片讀出，寫入到外部存儲器，再通過 VGA、LCD 等顯示。本實驗如果通過液晶屏顯示，需要有液晶屏模塊。2 實驗原理在前面的實驗中我們在 VGA、LCD 上顯示的是彩條，是 FPGA 內部產生的數據，本實驗將彩條替換為 SD 內的 BMP 圖片數據，但是 SD 卡讀取速度遠遠不能滿足顯示速度的要求，只能先寫入外部高速 RAM，再讀出后給視頻時序模塊顯示module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24
標簽： fpga
上傳時間： 2021-10-27
上傳用戶：
AT89S52-24單片機最小系統開發板ALTIUM設計硬件原理圖+PCB文件,2層板設計，大小為121x149mm，Altium Designer 設計的工程文件，包括完整的原理圖及PCB文件，可以用Altium(AD)軟件打開或修改，可作為你的產品設計的參考。主要器件型號列表如下：Library Component Count : 14Name Description----------------------------------------------------------------------------------------------------AT89S52-P 8 位微處理器/40引腳CAP CapacitorCAPACITOR POL CapacitorCRYSTAL CrystalD Connector 9 Receptacle Assembly, 9 Position, Right AngleHeader 2 Header, 2-PinHeader 4 Header, 4-PinHeader 5X2 Header, 5-Pin, Dual rowLED MAX232PZ_9 排針——9RES2SW-DPST Double-Pole, Single-Throw SwitchSW-PB Switch
上傳時間： 2021-11-17
上傳用戶：
AT89S52單片機主8入8出繼電器工控主板ALTIUM設計硬件原理圖+PCB文件,2層板設計，大小為121x149mm，Altium Designer 設計的工程文件，包括完整的原理圖及PCB文件，可以用Altium(AD)軟件打開或修改，可作為你的產品設計的參考。主要器件型號列表如下：Library Component Count : 25Name Description----------------------------------------------------------------------------------------------------24LC02AJKG 按鍵開關AT89S52-P 8 位微處理器/40引腳CAP CapacitorCAPACITOR POL CapacitorCPDR 瓷片電容CRYSTAL CrystalD Connector 9 Receptacle Assembly, 9 Position, Right AngleDG 電感DJDR 電解電容GO 光耦Header 5X2 Header, 5-Pin, Dual rowJDQYCK 繼電器——1常開1常閉LED 發光二極管LM2576HVT-3.3 Simple Switcher 3A Step Down Voltage RegulatorMAX232 NPN NPN Bipolar TransistorPZ_2 排針——2PZ_3 排針——3RES2Res 電阻Res PZ_8 8位排阻SW-DPST Double-Pole, Single-Throw SwitchWY2JG 穩壓二級管ZL2JG 整流二極管
上傳時間： 2021-11-17
上傳用戶：kingwide
STM32F407單片機開發板PDF原理圖+AD集成封裝庫+主要器件技術手冊資料:AD集成封裝庫列表：Library Component Count : 54Name Description----------------------------------------------------------------------------------------------------24C256 AMS1117ATK-HC05 ATK-HC05BAT BEEP BUTTONC CAPCH340G USB2UARTDDB9 DHT11 數字溫濕度傳感器HEAD2HEAD2*22 HR911105 HS0038Header 16 Header, 16-PinHeader 2 Header, 2-PinHeader 2X2 Header, 2-Pin, Dual rowHeader 3X2 Header, 3-Pin, Dual rowHeader 4 Header, 4-PinHeader 9X2 Header, 9-Pin, Dual rowIS62WV51216 JTAG KEY_M L LAN8720 ETH PHYLED2 Typical RED, GREEN, YELLOW, AMBER GaAs LEDLSENS LIGHT SENSL_SOP MAX3232 MAX3485 MIC MOS-P IRLML6401/SI2301MP2359 DC DC Step Down ICMPU6050 9軸運動處理傳感器NPN 8050/BCW846/BCW847NRF24L01 PHONE_M PNP 8550/BCW68POW R SMBJ TVSSN65HVD230D STM32F407ZET6 STM32F407ZET6TEST-POINT 測試點TFT_LCD TPAD ALIENTEK TPADUSB5USB_A_90 USB-A-90W25X16
上傳時間： 2021-12-15
上傳用戶：ttalli
FPGA讀取OV5640攝像頭數據并通過VGA或LCD屏顯示輸出的Verilog邏輯源碼Quartus工程文件+文檔說明，FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上傳時間： 2021-12-18
上傳用戶：
基于FPGA設計的sdram讀寫測試實驗Verilog邏輯源碼Quartus工程文件+文檔說明，DRAM選用海力士公司的 HY57V2562 型號,容量為的 256Mbit,采用了 54 引腳的TSOP 封裝, 數據寬度都為 16 位, 工作電壓為 3.3V,并丏采用同步接口方式所有的信號都是時鐘信號。FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
標簽： fpga sdram verilog quartus
上傳時間： 2021-12-18
上傳用戶：
黑金CYCLONE4 EP4CE6F17C8 FPGA開發板ALTIUM設計硬件工程（原理圖+PCB+AD集成封裝庫）,Altium Designer 設計的工程文件，包括完整的原理圖及PCB文件，可以用Altium(AD)軟件打開或修改，可作為你產品設計的參考。集成封裝器件型號列表：Library Component Count : 50Name Description----------------------------------------------------------------------------------------------------1117-3.3 24LC04B_0 4148 BAV99 CAP NP_Dup2CAP NP_Dup2_1 CAP NP_Dup2_2CP2102_0 C_Dup1 C_Dup1_1C_Dup2 C_Dup3 C_Dup4 C_Dup4_1 Circuit Breaker Circuit BreakerConnector 15 Receptacle Assembly, 15-Pin, Sim Line ConnectorDS1302_8SO EC EP4CE6F17C8 Cyclone IV Family FPGA, 2V Core, 179 I/O Pins, 2 PLLs, 256-Pin FBGA, Speed Grade 8, Commercial GradeEP4CE6F17C8_1 Cyclone IV Family FPGA, 2V Core, 179 I/O Pins, 2 PLLs, 256-Pin FBGA, Speed Grade 8, Commercial GradeFuse 2 FuseHEX6HY57651620/SO_0 Header 2 Header, 2-PinHeader 9X2 Header, 9-Pin, Dual rowINDUCTOR JTAG-10_Dup1 KEYB LED LED_Dup1 M25P16-VMN3PB 16 Mb (x1) Automotive Serial NOR Flash Memory, 75 MHz, 2.7 to 3.6 V, 8-pin SO8 Narrow (MN), TubeMHDR2X20 Header, 20-Pin, Dual rowMiniUSBB OSCPNP R RESISTOR RN RN_Dup1 R_Dup1 R_Dup2 R_Dup3 R_Dup5R_Dup6 SD SPEAKERSRV05-4SW KEY-DPDT ZTAbattery
標簽： 黑金 cyclone4 ep4ce6f17c8 fpga
上傳時間： 2021-12-22
上傳用戶：
TMS320F28035 DSP最小核心板開發板ALTIUM設計原理圖，無PCB板圖。原理圖已在項目中使用，包括CAN通信電路和瓷隔離電路等，可以做為你的設計參考，所用器件型號如下：ADUM1201AT24CXXBAV99 R26010005CAP CapacitorHeader 4 Header, 4-PinHeader 4X2 Header, 4-Pin, Dual rowINDUCTORL2 LM317 R25040043NTC R27040030OPTOISORES R20190049RES1 SN65HVD230/SO8SW-SPST Single-Pole, Single-Throw SwitchTL431TMS320F28035-80XTAL Crystal Oscillator
標簽： tms320f28035 dsp
上傳時間： 2021-12-22
上傳用戶：trh505
