Short description: GUI Ant-Miner is a tool for extracting classification rules from data. It is an updated version of a data mining algorithm called Ant-Miner (Ant Colony-based Data Miner), which was proposed in 2002 by Parpinelli, Lopes and Freitas. GUI Ant-Miner differs from the original algorithm as follows: It has a friendly graphical user interface, makes possible the use of ant populations within the Ant Colony Optimization (ACO) concept, data input file is standardized with the well-known Weka system, and runs on virtually any operating system since it is written in Java.
標(biāo)簽： classification description extracting Ant-Miner
上傳時(shí)間： 2013-12-18
上傳用戶：gonuiln
BGP-Broder Gateway Protocol which is a set rules govern by some functions which interconnects 2 autonomous systems.
標(biāo)簽： which interconnects BGP-Broder functions
上傳時(shí)間： 2017-07-29
上傳用戶：gxf2016
The goal of this thesis is the development of traffic engineering rules for cellular packet radio networks based on GPRS and EDGE. They are based on traffic models for typical mobile applications. Load generators, representing these traffic models, are developed and integrated into a simulation environment with the prototypical implementation of the EGPRS protocols and models for the radio channel, which were also developed in the framework of this thesis. With this simulation tool a comprehensive performance evaluation is carried out that leads to the traffic engineering rules.
標(biāo)簽： development engineering cellular traffic
上傳時(shí)間： 2014-01-11
上傳用戶：Miyuki
Logic2007中文教程 PADS Logic功能，特點(diǎn)及使用教程 本教程描述了PADS Logic 的各種功能和特點(diǎn)、以及使用方法。這些功 能包括： 如何在PADS Logic 中使用工作區(qū)(Working Area)。 如何在PADS Logic 的元件庫(kù)中定義目標(biāo)庫(kù)(Library)。 如何從庫(kù)中搜索有關(guān)的元件(Part)。 如何添加連線(Connection)、總線(Bus)、使用頁(yè)間連接符號(hào) 移動(dòng)(Move)、拷貝(Copy)、刪除(Delete)和編輯(Edit)等操作方式(Mode)。 在設(shè)計(jì)數(shù)據(jù)編輯時(shí)使用查詢/修改(Query/Modify)命令。 如何定義設(shè)計(jì)規(guī)則(Design rules)。 如何建立網(wǎng)表(Netlist)和SPICE 格式網(wǎng)絡(luò)表以及材料清單(BOM)報(bào)
上傳時(shí)間： 2013-04-24
上傳用戶：zhaoq123
在AD PCB 環(huán)境下，Design>rules>Plane> Polygon Connect style ,點(diǎn)中Polygon Connect style，右鍵點(diǎn)擊new rule ---新建一個(gè)規(guī)則點(diǎn)擊新建的規(guī)則既選中該規(guī)則，在name 框中改變里面的內(nèi)容即可修改該規(guī)則的名稱(chēng)，默認(rèn)是PolygonConnect_1 ，現(xiàn)我們修改為GND-Via.
上傳時(shí)間： 2013-10-29
上傳用戶：yunfan1978
Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
上傳時(shí)間： 2013-10-22
上傳用戶：ztj182002
Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
上傳時(shí)間： 2013-11-21
上傳用戶：不懂夜的黑
在AD PCB 環(huán)境下，Design>rules>Plane> Polygon Connect style ,點(diǎn)中Polygon Connect style，右鍵點(diǎn)擊new rule ---新建一個(gè)規(guī)則點(diǎn)擊新建的規(guī)則既選中該規(guī)則，在name 框中改變里面的內(nèi)容即可修改該規(guī)則的名稱(chēng)，默認(rèn)是PolygonConnect_1 ，現(xiàn)我們修改為GND-Via.
上傳時(shí)間： 2014-08-06
上傳用戶：leixinzhuo
dasniff daSniff is an open source customizable sniffer for win32 systems. It helps you to log your LAN traffic by specifying packet rules as filters.
標(biāo)簽： customizable dasniff daSniff sniffer
上傳時(shí)間： 2013-12-19
上傳用戶：invtnewer
Description: C4.5Rule-PANE is a rule learning method which could generate accurate and comprehensible symbolic rules, through regarding a neural network ensemble as a pre-process of a rule inducer. Reference: Z.-H. Zhou and Y. Jiang. Medical diagnosis with C4.5 rule preceded by artificial neural network ensemble. IEEE Transactions on Information Technology in Biomedicine, 2003, vol.7, no.1, pp.37-42. 使用神經(jīng)網(wǎng)絡(luò)集成方法診斷糖尿病,肝炎,乳腺癌癥的案例研究.
標(biāo)簽： comprehensibl Description Rule-PANE accurate
上傳時(shí)間： 2013-11-30
上傳用戶：wcl168881111111
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