unix或linux下的DNA分析軟件源碼 其功能如下 1. Edit up to 256 peptide or DNA sequences simultaneously. 2. Translates DNA->protein click next to display next frame. 3. Dot matrix plot of any 2 sequences. 4. Rudimentary amino acid statistics (MW and amino acid percentage) 5. Saves matrix plot as PBM image format. 6. Sequence reversal. 7. Creates alignment file for highlight (below). 8. Tab key toggles editing of next sequence.
標簽： simultaneously DNA sequences Transla
上傳時間： 2013-12-13
上傳用戶：lwwhust
The Ntrip RTCM Multiclient "NtripRTCMMC" simultaneously reads a number of real-time RTK data streams in RTCM 2.x format (basicly message types 18 and 19) as received from an Ntrip Broadcaster. It decodes the streams and generates raw and RINEX files.
標簽： simultaneously Multiclient NtripRTCMMC real-time
上傳時間： 2015-11-15
上傳用戶：一諾88
It s time for web servers to handle ten thousand clients simultaneously, don t you think? After all, the web is a big place now
標簽： simultaneously thousand clients servers
上傳時間： 2013-12-30
上傳用戶：wlcaption
This approach addresses two difficulties simultaneously: 1) the range limitation of mobile robot sensors and 2) the difficulty of detecting buildings in monocular aerial images. With the suggested method building outlines can be detected faster than the mobile robot can explore the area by itself, giving the robot an ability to “see” around corners. At the same time, the approach can compensate for the absence of elevation data in segmentation of aerial images. Our experiments demonstrate that ground-level semantic information (wall estimates) allows to focus the segmentation of the aerial image to find buildings and produce a ground-level semantic map that covers a larger area than can be built using the onboard sensors.
標簽： simultaneously difficulties limitation addresses
上傳時間： 2014-06-11
上傳用戶：waitingfy
displayes two webcam simultaneously
標簽： simultaneously displayes webcam two
上傳時間： 2014-08-19
上傳用戶：as275944189
The 14-bit LTC2351-14 is a 1.5Msps, low power SARADC with six simultaneously sampled differential inputchannels. It operates from a single 3V supply and featuressix independent sample-and-hold amplifi ers and a singleADC. The single ADC with multiple S/HAs enables excellentrange match (1mV) between channels and channel-tochannelskew (200ps).
上傳時間： 2014-12-23
上傳用戶：天誠24
The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.
上傳時間： 2013-11-01
上傳用戶：dingdingcandy
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-14
上傳用戶：fdmpy
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-23
上傳用戶：shen_dafa
The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.
上傳時間： 2013-10-09
上傳用戶：evil
