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  • 智能天線技術在基站中的應用

    為了能夠滿足基站易于選址、優(yōu)質快速的建站要求和易維護、低成本、高可靠的運行要求,本文對以方艙來實現(xiàn)一體化結構基站做出一番探討。從系統(tǒng)設計的觀點闡述了移動通信高性能基站天線設計的幾個關鍵問題,介紹了智能天線技術在基站中的應用,并且用HFSS軟件仿真了一種新型的對稱陣子天線,該天線駐波比小于2的帶寬可以達到60%,具有良好的寬頻帶特性。 Abstract:  In order to meet the station construction requirement of easy site selection and fast base station, and meet the operational requirement of easy maintenance, low cost and high reliability, this paper discussed the unified architecture base station using shelter. Several key problems of high performance mobile communication base station antenna were illustrated from the view of system design, the application of smart antenna in base station was also introduced. And a novel dipole antenna was simulated by using HFSS, the VSWR of the antenna is less than 2, and the bandwidth was reach to 60%. So it has good broadband properties.

    標簽: 智能天線 基站 中的應用

    上傳時間: 2013-11-20

    上傳用戶:linlin

  • 軌道交通系統(tǒng)中列車定位技術

       闡述了軌道交通列車定位技術。介紹了在軌道交通系統(tǒng)中列車定位技術的功能,國內外軌道交通中主要采用的列車定位方法,重點論述了幾種主要定位技術,并從定位精度、閉塞制式、維護投資成本、抗干擾等方面進行分析比較。提出目前軌道交通定位技術應綜合運用,取長補短,多種方法相互融合,才能滿足軌道交通中對安全可靠性的要求。 Abstract:  Rail train positioning technology is described. The paper introduces the funetions of the train positioning technology in the rail transit system, the main methods of train positioning do mestic and international rail, and focuses on several key methods, analyzes and compares from the positioning accuracy, block system, maintenance and investment cost, interference and so on, suggested that the current rail positioning technology should be integrated use of positioning method of meriging, learn from each other, to meet the reliability requirements of rail safety.

    標簽: 軌道交通 列車 定位技術

    上傳時間: 2013-11-25

    上傳用戶:franktu

  • UHF讀寫器設計中的FM0解碼技術

       針對UHF讀寫器設計中,在符合EPC Gen2標準的情況下,對標簽返回的高速數(shù)據(jù)進行正確解碼以達到正確讀取標簽的要求,提出了一種新的在ARM平臺下采用邊沿捕獲統(tǒng)計定時器數(shù)判斷數(shù)據(jù)的方法,并對FM0編碼進行解碼。與傳統(tǒng)的使用定時器定時采樣高低電平的FM0解碼方法相比,該解碼方法可以減少定時器定時誤差累積的影響;可以將捕獲定時器數(shù)中斷與數(shù)據(jù)判斷解碼相對分隔開,使得中斷對解碼影響很小,實現(xiàn)捕獲與解碼的同步。通過實驗表明,這種方法提高了解碼的效率,在160 Kb/s的接收速度下,讀取一張標簽的時間約為30次/s。 Abstract:  Aiming at the requirement of receiving correctly decoded data from the tag under high-speed communication which complied with EPC Gen2 standard in the design of UHF interrogator, the article introduced a new technology for FM0 decoding which counted the timer counter to judge data by using the edge interval of signal capture based on the ARM7 platform. Compared with the traditional FM0 decoding method which used the timer timed to sample the high and low level, the method could reduce the accumulation of timing error and could relatively separate capture timer interrupt and the data judgment for decoding, so that the disruption effect on the decoding was small and realizd synchronization of capture and decoding. Testing result shows that the method improves the efficiency of decoding, at 160 Kb/s receiving speed, the time of the interrogator to read a tag is about 30 times/s.

    標簽: UHF FM0 讀寫器 解碼技術

    上傳時間: 2013-11-10

    上傳用戶:liufei

  • 差分電路中單端及混合模式S-參數(shù)的使用

    Single-Ended and Differential S-Parameters Differential circuits have been important incommunication systems for many years. In the past,differential communication circuits operated at lowfrequencies, where they could be designed andanalyzed using lumped-element models andtechniques. With the frequency of operationincreasing beyond 1GHz, and above 1Gbps fordigital communications, this lumped-elementapproach is no longer valid, because the physicalsize of the circuit approaches the size of awavelength.Distributed models and analysis techniques are nowused instead of lumped-element techniques.Scattering parameters, or S-parameters, have beendeveloped for this purpose [1]. These S-parametersare defined for single-ended networks. S-parameterscan be used to describe differential networks, but astrict definition was not developed until Bockelmanand others addressed this issue [2]. Bockelman’swork also included a study on how to adapt single-ended S-parameters for use with differential circuits[2]. This adaptation, called “mixed-mode S-parameters,” addresses differential and common-mode operation, as well as the conversion betweenthe two modes of operation.This application note will explain the use of single-ended and mixed-mode S-parameters, and the basicconcepts of microwave measurement calibration.

    標簽: 差分電路 單端 模式

    上傳時間: 2014-03-25

    上傳用戶:yyyyyyyyyy

  • 基于(英蓓特)STM32V100的看門狗程序

    This example shows how to update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI). The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDGISR the counter is refreshed to prevent a WWDG reset and led connected to PC.07is toggled.The EXTI line9 is connected to PB.09 pin and configured to generate an interrupton falling edge.In the NVIC, EXTI line9 to 5 interrupt vector is enabled with priority equal to 0and the WWDG interrupt vector is enabled with priority equal to 1 (EXTI IT > WWDG IT). The EXTI Line9 will be used to simulate a software failure: once the EXTI line9event occurs (by pressing Key push-button on EVAL board) the correspondent interruptis served, in the ISR the led connected to PC.07 is turned off and the EXTI line9pending bit is not cleared. So the CPU will execute indefinitely EXTI line9 ISR andthe WWDG ISR will never be entered(WWDG counter not updated). As result, when theWWDG counter falls to 3Fh the WWDG reset occurs.If the EXTI line9 event don抰 occurs the WWDG counter is indefinitely refreshed inthe WWDG ISR which prevent from WWDG reset. If the WWDG reset is generated, after resuming from reset a led connected to PC.06is turned on. In this example the system is clocked by the HSE(8MHz).

    標簽: V100 STM 100 32V

    上傳時間: 2013-11-11

    上傳用戶:gundamwzc

  • c++入門經(jīng)典第3三版下載(附源代碼)

    C++在幾乎所有的計算環(huán)境中都非常普及,而且可以用于幾乎所有的應用程序。C++從C中繼承了過程化編程的高效性,并集成了面向對象編程的功能。C++在其標準庫中提供了大量的功能。有許多商業(yè)C++庫支持數(shù)量眾多的操作系統(tǒng)環(huán)境和專業(yè)應用程序。但因為它的內容太多了,所以掌握C++并不十分容易。本書詳述了C++語言的各個方面,包括數(shù)據(jù)類型、程序控制、函數(shù)、指針、調試、類、重載、繼承、多態(tài)性、模板、異常和輸入輸出等內容。每一章都以前述內容為基礎,每個關鍵點都用具體的示例進行詳細的講解。本書基本不需要讀者具備任何C++知識,書中包含了理解C++的所有必要知識,讀者可以從頭開始編寫自己的C++程序。本書也適合于具備另一種語言編程經(jīng)驗但希望全面掌握C++語言的讀者。 I created all the files under Microsoft Windows so lines are terminated by CR/LF. In addition to this "ReadMe" file you will find three zip archives in the primary archive, so you need to unzip each of these to get at the code. 為PDG格式,這有pdg閱讀器下載|pdg文件閱讀器下載

    標簽: 源代碼

    上傳時間: 2013-11-18

    上傳用戶:gaoqinwu

  • 便攜式超聲系統(tǒng)中的Xilinx器件

    There has long been a need for portable ultrasoundsystems that have good resolution at affordable costpoints. Portable systems enable healthcare providersto use ultrasound in remote locations such asdisaster zones, developing regions, and battlefields,where it was not previously practical to do so.

    標簽: Xilinx 便攜式 超聲系統(tǒng) 器件

    上傳時間: 2015-01-01

    上傳用戶:hfnishi

  • 周立功:SOPC嵌入式系統(tǒng)實驗教程(一)部分章節(jié)及實驗代碼

      SOPC嵌入式系統(tǒng)實驗教程(一)【作者:周立功;出版社:北京航空航天大學出版社】(因網(wǎng)上資料有限,所以本資料為周立功 SOPC嵌入式系統(tǒng)實驗教程(一)部分章節(jié)及實驗代碼,真心想學的可以買一本書看看。)   該書是與《SOPC嵌入式系統(tǒng)基礎教程》相配套的實驗教材。設計開發(fā)了 45個實驗,包括SOPC硬件系統(tǒng)的基礎實驗,基于Nios II外設的基礎編程實驗,基于實驗箱外設的Nios II高級編程實驗,在Nios II系統(tǒng)中進行基于μ C/OS-II操作系統(tǒng)的應用程序開發(fā)實驗和SOPC硬件系統(tǒng)的高級實驗。各種實驗的安排由淺人深,由硬件到軟件,相對完整,使讀者很容易學習和掌握SO PC嵌入式系統(tǒng)的開發(fā)應用。

    標簽: SOPC 嵌入式系統(tǒng) 實驗教程

    上傳時間: 2013-11-01

    上傳用戶:superman111

  • Analog Solutions for Altera FPGAs

    Designing withProgrammable Logicin an Analog WorldProgrammable logic devices revolutionizeddigital design over 25 years ago,promising designers a blank chip todesign literally any function and programit in the field. PLDs can be low-logicdensity devices that use nonvolatilesea-of-gates cells called complexprogrammable logic devices (CPLDs)or they can be high-density devicesbased on SRAM look-up tables (LUTs)

    標簽: Solutions Analog Altera FPGAs

    上傳時間: 2013-10-27

    上傳用戶:fredguo

  • XAPP806 -決定DDR反饋時鐘的最佳DCM相移

    This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.

    標簽: XAPP 806 DDR DCM

    上傳時間: 2014-11-26

    上傳用戶:erkuizhang

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