Design techniques for electronic systems areconstantly changing. In industries at the heart of thedigital revolution, this change is especially acute.Functional integration, dramatic increases incomplexity, new standards and protocols, costconstraints, and increased time-to-market pressureshave bolstered both the design challenges and theopportunities to develop modern electronic systems.One trend driving these changes is the increasedintegration of core logic with previously discretefunctions to achieve higher performance and morecompact board designs.
標(biāo)簽： System Xilinx FPGA 151
上傳時間： 2013-11-23
上傳用戶：kangqiaoyibie
The standard that governs the design of avioniccomponents and systems, DO-254, is one of the mostpoorly understood but widely applicable standardsin the avionic industry. While information on thegeneral aspects of the standard is easy to obtain, thedetails of exactly how to implement the standard aresketchy. And once an entity develops a process thatachieves compliance, the details of how compliancewas achieved become part of the intellectualproperty of that entity. This white paper focuses onthe details of developing a DO-254 compliantprocess for the design of FPGAs.
上傳時間： 2013-11-03
上傳用戶：ysystc670
XAPP520將符合2.5V和3.3V I/O標(biāo)準(zhǔn)的7系列FPGA高性能I/O Bank進(jìn)行連接 The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
上傳時間： 2013-11-06
上傳用戶：wentianyou
The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.
標(biāo)簽： xilinx Zynq 7000 EPP
上傳時間： 2013-10-09
上傳用戶：evil
隨著PCB設(shè)計(jì)復(fù)雜程度的不斷提高，設(shè)計(jì)工程師對 EDA工具在交互性和處理復(fù)雜層次化設(shè)計(jì)功能的要求也越來越高。Cadence Design Systems, Inc. 作為世界第一的EDA工具供應(yīng)商，在這些方面一直為用戶提供業(yè)界領(lǐng)先的解決方案。在 Concept-HDL15.0中，這些功能又得到了大度地提升。首先，Concept-HDL15.0，提供了交互式全局屬性修改刪除，以及全局器件替換的圖形化工作界面。在這些全新的工作環(huán)境中，用戶可以在圖紙，設(shè)計(jì)，工程不同的級別上對器件，以及器件/線網(wǎng)的屬性進(jìn)行全局性的編輯。
上傳時間： 2013-11-12
上傳用戶：ANRAN
針對嵌入式機(jī)器視覺系統(tǒng)向獨(dú)立化、智能化發(fā)展的要求，介紹了一種嵌入式視覺系統(tǒng)--智能相機(jī)。基于對智能相機(jī)體系結(jié)構(gòu)、組成模塊和圖像采集、傳輸和處理技術(shù)的分析，對國內(nèi)外的幾款智能相機(jī)進(jìn)行比較。綜合技術(shù)發(fā)展現(xiàn)狀，提出基于FPGA+DSP模式的硬件平臺，并提出智能相機(jī)的發(fā)展方向。分析結(jié)果表明，該系統(tǒng)設(shè)計(jì)可以實(shí)現(xiàn)脫離PC運(yùn)行，完成圖像獲取與分析，并作出相應(yīng)輸出。 Abstract: This paper introduced an embedded vision system-intelligent camera ，which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera architecture， component modules and image acquisition， transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad， the paper proposed the hardware platform based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design， the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding output.
標(biāo)簽： FPGA DSP 模式 智能相機(jī)
上傳時間： 2013-11-14
上傳用戶：無聊來刷下
Prakash Rashinkar has over 15 years experience in system design and verificationof embedded systems for communication satellites, launch vehicles and spacecraftground systems, high-performance computing, switching, multimedia, and wirelessapplications. Prakash graduated with an MSEE from Regional Engineering College,Warangal, in India. He lead the team that was responsible for delivering themethodologies for SOC verification at Cadence Design Systems. Prakash is anactive member of the VSIA Functional Verification DWG. He is currently Architectin the Vertical Markets and Design Environments Group at Cadence.
上傳時間： 2013-11-19
上傳用戶：m62383408
第一章 傳輸線理論一 傳輸線原理二 微帶傳輸線三 微帶傳輸線之不連續(xù)分析第二章 被動組件之電感設(shè)計(jì)與分析一 電感原理二 電感結(jié)構(gòu)與分析三 電感設(shè)計(jì)與模擬四 電感分析與量測傳輸線理論與傳統(tǒng)電路學(xué)之最大不同，主要在于組件之尺寸與傳導(dǎo)電波之波長的比值。當(dāng)組件尺寸遠(yuǎn)小于傳輸線之電波波長時，傳統(tǒng)的電路學(xué)理論才可以使用，一般以傳輸波長（Guide wavelength）的二十分之ㄧ（λ/20）為最大尺寸，稱為集總組件（Lumped elements）；反之，若組件的尺寸接近傳輸波長，由于組件上不同位置之電壓或電流的大小與相位均可能不相同，因而稱為散布式組件（Distributed elements）。 由于通訊應(yīng)用的頻率越來越高，相對的傳輸波長也越來越小，要使電路之設(shè)計(jì)完全由集總組件所構(gòu)成變得越來越難以實(shí)現(xiàn)，因此，運(yùn)用散布式組件設(shè)計(jì)電路也成為無法避免的選擇。 當(dāng)然，科技的進(jìn)步已經(jīng)使得集總組件的制作變得越來越小，例如運(yùn)用半導(dǎo)體制程、高介電材質(zhì)之低溫共燒陶瓷（LTCC）、微機(jī)電（MicroElectroMechanical Systems, MEMS）等技術(shù)制作集總組件，然而，其中電路之分析與設(shè)計(jì)能不乏運(yùn)用到散布式傳輸線的理論，如微帶線（Microstrip Lines）、夾心帶線（Strip Lines）等的理論。因此，本章以討論散布式傳輸線的理論開始，進(jìn)而以微帶傳輸線為例介紹其理論與公式，并討論微帶傳輸線之各種不連續(xù)之電路，以作為后續(xù)章節(jié)之被動組件的運(yùn)用。
標(biāo)簽： 傳輸線
上傳時間： 2013-11-10
上傳用戶：瀟湘書客
8051參考設(shè)計(jì)，與其他8051的免費(fèi)IP相比，文檔相對較全，Oregano System 提供 This is version 1.3 of the MC8051 IP core. September 2002: Oregano Systems - Design & Consulting GesmbH Change history: - Improved tb_mc8051_siu_sim.vhd to verify duplex operation. - Corrected problem with duplex operation in file mc8051_siu_rtl.vhd
上傳時間： 2013-11-06
上傳用戶：XLHrest
a8259 可編程中斷控制 altera提供 The a8259 is designed to simplify the implementation of the interrupt interface in 8088 and 8086 based microcomputer systems. The device is known as a programmable interrupt controller. The a8259 receives and prioritizes up to 8 interrupts, and in the cascade mode, this can be expanded up to 64 interrupts. An asynchronous reset and a clock input have been added to improve operation and reliability.
上傳時間： 2015-01-02
上傳用戶：panpanpan
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