1)Learn more about the capabilities in Quartus: 2)Learn to use different design entry techniques 2)Design entry methods available within Quartus Text editor,Block diagram/schematic file editor, Quartus interface with design entry/synthesis tools from Exemplar, Synopsys, Synplicity and Viewlogic
標簽： Learn capabilities techniques different
上傳時間： 2014-01-18
上傳用戶：yxgi5
This demo nstrates the use of the reversible jump MCMC simulated annealing for neural networks. This algorithm enables us to maximise the joint posterior distribution of the network parameters and the number of basis function. It performs a global search in the joint space of the parameters and number of parameters, thereby surmounting the problem of local minima. It allows the user to choose among various model selection criteria, including AIC, BIC and MDL
標簽： This reversible annealing the
上傳時間： 2015-07-19
上傳用戶：ma1301115706
use swarm intelligence algorithm to slove travelling sales man problems in matlab
標簽： intelligence travelling algorithm problems
上傳時間： 2013-12-20
上傳用戶：問題問題
use genetic ant algorithm to slove TSP problem
標簽： algorithm genetic problem slove
上傳時間： 2013-12-26
上傳用戶：小碼農lz
use swarm intelligence to simulate network routings in omnet
標簽： intelligence simulate routings network
上傳時間： 2014-06-16
上傳用戶：zyt
xletview, for UNIX file and directory names are case sensitive. The path to the project CVSROOT must be specified using lowercase characters (i.e. /cvsroot/xletview)
標簽： directory sensitive xletview CVSROOT
上傳時間： 2013-12-18
上傳用戶：miaochun888
Easy to use SMS/MMS Messaging Gateway to develop Content Delivery Platforms by GSM Operators,Content Providers and even non-telecom guys. Uses file system for data flow.Written for .NET 2.0 in C#
標簽： Content Messaging Platforms Operators
上傳時間： 2014-01-01
上傳用戶：1109003457
not use Java API to produce two simple java implementation of a dictionary interface, LinkedListDictionary and HashDictionary, that maps a String key to an Object value
標簽： implementation LinkedListDict dictionary interface
上傳時間： 2015-07-25
上傳用戶：黃華強
turbo jtag CPLD source code use altera EPM7128S
上傳時間： 2015-07-26
上傳用戶：685
關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標簽： investigates implementing pipelines circuits
上傳時間： 2015-07-26
上傳用戶：CHINA526
