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vector-processor

  • This document describes how to switch to and program the unisersal serial bus (USB) analog phase-lo

    This document describes how to switch to and program the unisersal serial bus (USB) analog phase-locked loop (APLL) on the C5506/C5507/C5509A devices. Example assembly programs for programming and switching to and from the APLL are also provided in the attached zip file. It is assumed that the reader is familiar with the use and operation of the C5506/C5507/C5509A USB digital phase-locked loop (DPLL) and C55x™ Digital Signal Processor (DSP) IDLE procedures.

    標簽: describes unisersal document phase-lo

    上傳時間: 2014-01-13

    上傳用戶:hustfanenze

  • The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontro

    The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontroller. It is not, and is not intended as, a high fidelity circuit simulation. This package includes the following files. Note that the license agreement is stated in the main VHDL file, PICCPU.VHD and common questions are answered in the file SYNTHPIC.TXT Files: README.TXT This file.. SYNTHPIC.TXT Questions and Answers PICCPU.VHD Main processor VHDL file PICALU.VHD ALU for the PICCPU PICREGS.VHD Data memory PICROM.VHD Program memory (created by HEX2VHDL utility) PICTEST.VHD Simple test bench I used to do testing (optional) PICTEST.CMD My Viewlogic ViewSim command file (again, optional) TEST1.ASM First program I assembled and ran on it. TEST2.ASM Another test program.. TEST3.ASM Yet another.. TEST4.ASM Yet another.. TEST5.ASM Yet another.. TEST6.ASM Yet another.. HEX2VHDL.CPP Utility for converting

    標簽: synthesizable microcontro Synthetic PIC

    上傳時間: 2013-12-22

    上傳用戶:妄想演繹師

  • FDMP the body of the kernel, the Information-Technology Promotion Agency (IPA) adopted by the unexpl

    FDMP the body of the kernel, the Information-Technology Promotion Agency (IPA) adopted by the unexplored themes of Creativity software is one of the "multi-processor system-level development environment for the development of the system" as part of the development Susumu Honda也氏Was responsible.

    標簽: the Information-Technology Promotion adopted

    上傳時間: 2013-12-25

    上傳用戶:dengzb84

  • pccard driver s3c2440.The S3C2440A offers outstanding features with its CPU core, a 16/32-bit ARM92

    pccard driver s3c2440.The S3C2440A offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length.

    標簽: outstanding S3C2440A features pccard

    上傳時間: 2013-12-24

    上傳用戶:lizhen9880

  • 這是一個Quartus的工程文件和verilog代碼

    這是一個Quartus的工程文件和verilog代碼,講如何把memory 變成vector

    標簽: Quartus verilog 工程 代碼

    上傳時間: 2017-03-07

    上傳用戶:趙云興

  • In this project we analyze and design the minimum mean-square error (MMSE) multiuser receiver for un

    In this project we analyze and design the minimum mean-square error (MMSE) multiuser receiver for uniformly quantized synchronous code division multiple access (CDMA) signals in additive white Gaussian noise (AWGN) channels.This project is mainly based on the representation of uniform quantizer by gain plus additive noise model. Based on this model, we derive the weight vector and the output signal-to-interference ratio (SIR) of the MMSE receiver. The effects of quantization on the MMSE receiver performance is characterized in a single parameter named 鈥漞quivalent noise variance鈥? The optimal quantizer stepsize which maximizes the MMSE receiver output SNR is also determined.

    標簽: mean-square multiuser receiver project

    上傳時間: 2014-11-21

    上傳用戶:ywqaxiwang

  • Builder uses to integrate a larger system module. Each component consists of a structured set of fi

    Builder uses to integrate a larger system module. Each component consists of a structured set of files within a directory. The files in a component directory serve the following The RS232 UART Core implements a method for communication of serial data. The core provides a simple register-mapped Avalon廬 interface. Master peripherals [such as a Nios廬 II processor] communicate with the core by reading and writing control and data registers.

    標簽: structured integrate component consists

    上傳時間: 2014-01-15

    上傳用戶:lnnn30

  • 一個全排列算法的實現

    一個全排列算法的實現,利用了C++模板技術以及STL 中的 Vector

    標簽: 算法

    上傳時間: 2013-12-29

    上傳用戶:gmh1314

  • The driver supports both the 16F and 18F families. The trick is that the driver carefully emulates t

    The driver supports both the 16F and 18F families. The trick is that the driver carefully emulates the hardware UART found in the PIC18F452 processor. This information has unfortunately misled some into thinking it does not work with the 16F family. During devlopment the driver was tested on a real PIC16F84A (as opposed to software emulation). To make sure nothing has been broken, I have just recompiled the code using SourceBoost 6.0 and it compiled without error.

    標簽: driver The carefully the

    上傳時間: 2013-12-19

    上傳用戶:diets

  • The files adi_ssl_init.h and adi_ssl_init.c are used to define the functions adi_ssl_Init()

    The files adi_ssl_init.h and adi_ssl_init.c are used to define the functions adi_ssl_Init() and 慳di_ssl_Terminate()?which initialize and terminate all the Blackfin System Services in the appropriate order, for a particular EZ-Kit, depending on the Blackfin processor used.

    標簽: adi_ssl_init adi_ssl_Init functions define

    上傳時間: 2014-01-21

    上傳用戶:sammi

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