a fat12 source code, it is verified for many platform
標簽： platform verified source code
上傳時間： 2015-04-28
上傳用戶：llandlu
Pre-designed and pre-verified hardware and software blocks can be combined on chips for many different applicationsVthey promise large productivity gains.
標簽： Pre-designed pre-verified and hardware
上傳時間： 2015-10-08
上傳用戶：凌云御清風
PCI設計指南The Xilinx LogiCORE PCI interface is a fully verified, pre-implemented PCI Bus interface. This interface is available in 32-bit and 64- bit versions, with support for multiple Xilinx FPGA device families. It is designed to support both Verilog-HDL and VHDL. The design examples in this book are provided in Verilog.
標簽： interface PCI pre-implemented LogiCORE
上傳時間： 2016-04-03
上傳用戶：清風冷雨
wireless stepper motor verified by kpserver
標簽： wireless kpserver verified stepper
上傳時間： 2013-12-23
上傳用戶：Zxcvbnm
針對使用硬件描述語言進行設計存在的問題，提出一種基于FPGA并采用DSP Builder作為設計工具的數字信號處理器設計方法。并按照Matlab/Simulink/DSP Builder/QuartusⅡ設計流程，設計了一個12階FIR 低通數字濾波器，通過Quartus 時序仿真及嵌入式邏輯分析儀SignalTapⅡ硬件測試對設計進行了驗證。結果表明，所設計的FIR 濾波器功能正確，性能良好。 Abstract: Aiming at the problems in designing DSP using HDL，a method of designing DSP based on FPGA which using DSP Builder as designed tool is pointed out.A 12-order low-pass FIR digital filter was designed according to the process of Matlab/Simulink/DSP Builder/QuartusⅡ, and the design was verified by the timing simulation based on QuartusⅡand practical test based on SignalTapⅡ. The result shows the designed filter is correct in function and good in performance.
上傳時間： 2013-11-17
上傳用戶：lo25643
BlueCore supports a mechanism called Device Firmware Upgrade (DFU) to enable its software and configuration data to be replaced. To guard against unauthorised changes, downloaded files can be verified by means of signatures. The DFU Tools are a suite of programs that enable firmware and persistent store files to be signed and combined to form DFU files.
標簽： mechanism BlueCore supports Firmware
上傳時間： 2015-12-04
上傳用戶：manking0408
THIS DESIGN IS PROVIDED TO YOU "AS IS". XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE. This design has not been verified on hardware (as opposed to simulations), and it should be used only as an example design, not as a fully functional core. XILINX does not warrant the performance, functionality, or operation of this Design will meet your requirements, or that the operation of the Design will be uninterrupted or error free, or that defects in the Design will be corrected. Furthermore, XILINX does not warrant or make any representations regarding use or the results of the use of the Design in terms of correctness, accuracy, reliability or otherwise.
標簽： CONDITIONS WARRANTIES YOU PROVIDED
上傳時間： 2016-03-21
上傳用戶：1427796291
The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM models. The design is verified with timing constraints at 115 MHZ.
標簽： SDRAM controller simulated designed
上傳時間： 2013-12-18
上傳用戶：yiwen213
This chapter contains sample programs for determining capacity. The reader is advised to go through the coding. The file "capacity_water.m" is for measuring the waterfilling capacity. It should be made to work with a file similar to "capacity_plot_main.m". The latter file deals with all the other capacity plots given in the book in Chapter 2. All programs are verified with MATLAB versions 6.0 and above with signal processing and communications toolboxes.
標簽： determining capacity contains programs
上傳時間： 2016-08-24
上傳用戶：yph853211
This is GPS Matlab findPreambles finds the first preamble occurrence in the bit stream of each channel. The preamble is verified by check of the spacing between preambles [6sec] and parity checking of the first two words in a subframe. At the same time function returns list of channels, that are in tracking state and with valid preambles in the nav data stream.
標簽： findPreambles occurrence the preamble
上傳時間： 2013-12-23
上傳用戶：秦莞爾w
