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verilog-A

是一本好書,verilog HDL,a guide to digital design and synthesis

是一本好書,verilog HDL,a guide to digital design and synthesis

標簽： synthesis verilog digital design

上傳時間： 2015-07-14

上傳用戶：熊少鋒
Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A c

Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm.

標簽： representation Magnitude the magnitude

上傳時間： 2013-12-24

上傳用戶：金宜
Verilog HDL Synthesis, A Practical Primer 學習Verilog HDL一本很不錯的英文書

Verilog HDL Synthesis, A Practical Primer 學習Verilog HDL一本很不錯的英文書，比較透徹

標簽： Verilog HDL Synthesis Practical

上傳時間： 2016-01-19

上傳用戶：hongmo
this is a verilog hdl language referance book , tell you the basic useage of this language.

this is a verilog hdl language referance book , tell you the basic useage of this language.

標簽： language this referance verilog

上傳時間： 2016-02-06

上傳用戶：日光微瀾
PacoBlaze is a from-scratch synthesizable & behavioral Verilog clone of Ken Chapman s popular PicoB

PacoBlaze is a from-scratch synthesizable & behavioral Verilog clone of Ken Chapman s popular PicoBlaze embedded microcontroller. by Pablo Bleyer Kocik

標簽： synthesizable from-scratch behavioral PacoBlaze

上傳時間： 2013-12-09

上傳用戶：hphh
vga verilog codes which design a pong game and output to vga monitor

vga verilog codes which design a pong game and output to vga monitor

標簽： vga verilog monitor design

上傳時間： 2013-12-31

上傳用戶：牛布牛
編寫verilog代碼利用實驗箱上的A/D芯片完成模數轉換。輸入電壓由實驗箱提供

編寫verilog代碼利用實驗箱上的A/D芯片完成模數轉換。輸入電壓由實驗箱提供，其幅值在0~5V間變化，由電位器控制。輸出信號顯示輸入的模擬電壓值，由數碼管顯示為2位BCD碼的形式。

標簽： verilog 實驗箱編寫代碼

上傳時間： 2013-12-16

上傳用戶：songnanhua
this a Uart source code using Verilog.

this a Uart source code using Verilog.

標簽： Verilog source using this

上傳時間： 2016-05-19

上傳用戶：zsjzc
This Verilog HDL description implements a UART Version 1.1 : Original Creation 2.1 : added commen

This Verilog HDL description implements a UART Version 1.1 : Original Creation 2.1 : added comments

標簽： description implements Creation Original

上傳時間： 2016-05-27

上傳用戶：1109003457
(2003 prentice-hall)verilog hdl：a guide to digital design and synthesis(2nd edition).rar

(2003 prentice-hall)verilog hdl：a guide to digital design and synthesis(2nd edition).rar

標簽： prentice-hall synthesis digital edition

上傳時間： 2014-01-17

上傳用戶：teddysha

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