verilog編寫隨機(jī)數(shù)產(chǎn)生源程序，在硬件電路設(shè)計(jì)中應(yīng)用廣泛。本程序是在LFSR and a CASR 基礎(chǔ)上實(shí)現(xiàn)的
標(biāo)簽： verilog 編寫 源程序 隨機(jī)數(shù)
上傳時(shí)間： 2016-10-19
上傳用戶：王小奇
verilog code 16-bit carry look-ahead adder output [15:0] sum // 相加總和 output carryout // 進(jìn)位 input [15:0] A_in // 輸入A input [15:0] B_in // 輸入B input carryin // 第一級(jí)進(jìn)位 C0
標(biāo)簽： output look-ahead carryout verilog
上傳時(shí)間： 2014-12-06
上傳用戶：ls530720646
MCPU is a minimal cpu aimed to fit into a 32 Macrocell CPLD - one of the smallest available programmable logic devices. While this CPU is not powerful enough for real world applications it has proven itself as a valuable educational tool. The source code is just a single page and easily understood. Both VHDL and Verilog versions are supplied. The package comes with assembler, emulator and extensive documentation.
標(biāo)簽： Macrocell available smallest programm
上傳時(shí)間： 2017-03-11
上傳用戶：mikesering
verilog的簡要教程 基本邏輯門，例如a n d、o r和n a n d等都內(nèi)置在語言中。 • 用戶定義原語（ U D P）創(chuàng)建的靈活性。用戶定義的原語既可以是組合邏輯原語，也可以 是時(shí)序邏輯原語。 • 開關(guān)級(jí)基本結(jié)構(gòu)模型，例如p m o s 和n m o s等也被內(nèi)置在語言中。
上傳時(shí)間： 2017-05-05
上傳用戶：1583060504
Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and different methodologies are compared using real-world examples.
標(biāo)簽： synchronous Designing engineer digital
上傳時(shí)間： 2014-01-17
上傳用戶：dreamboy36
數(shù)字下變頻的Verilog程序，測試可以直接使用，將A/D信號(hào)下變頻為基帶I，Q兩路信號(hào)
標(biāo)簽： Verilog 數(shù)字下變頻 程序
上傳時(shí)間： 2014-01-19
上傳用戶：saharawalker
This circuit is a nice edge detector that gives you synchronous notification of edges on your input signal. There s no excuse for not doing this it s a tiny circuit in just five lines of Verilog.
標(biāo)簽： notification synchronous detector circuit
上傳時(shí)間： 2017-09-18
上傳用戶：xieguodong1234
電子書-RTL Design Style Guide for Verilog HDL540頁A FF having a fixed input value is generated from the description in the upper portion of Example 2-21. In this case, ’0’ is output when the reset signal is asynchronously input, and ’1’ is output when the START signal rises. Therefore, the FF data input is fixed at the power supply, since the typical value ’1’ is output following the rise of the START signal. When FF input values are fixed, the fixed inputs become untestable and the fault detection rate drops. When implementing a scan design and converting to a scan FF, the scan may not be executed properl not be executed properly, so such descriptions , so such descriptions are not are not recommended. recommended.[1] As in the lower part of Example 2-21, be sure to construct a synchronous type of circuit and ensure that the clock signal is input to the clock pin of the FF. Other than the sample shown in Example 2-21, there are situations where for certain control signals, those that had been switched due to the conditions of an external input will no longer need to be switched, leaving only a FF. If logic exists in a lower level and a fixed value is input from an upper level, the input value of the FF may also end up being fixed as the result of optimization with logic synthesis tools. In a situation like this, while perhaps difficult to completely eliminate, the problem should be avoided as much as possible.
標(biāo)簽： RTL verilog hdl
上傳時(shí)間： 2022-03-21
上傳用戶：canderile
第八章 數(shù)字電路技術(shù) A／D,D／A
上傳時(shí)間： 2013-07-10
上傳用戶：eeworm
21世紀(jì)大學(xué)新型參考教材系列 集成電路A 荒井
上傳時(shí)間： 2013-07-20
上傳用戶：eeworm
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