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vsia

  • openmore/openmore vsia 評估程序、電子表格說媒文件

    openmore/openmore vsia 評估程序、電子表格說媒文件

    標簽: openmore vsia 程序 電子表格

    上傳時間: 2014-01-25

    上傳用戶:xc216

  • 數字集成電路與嵌入式內核系統可測試性設計(影印版)

    ·書中包括的索引使你能夠根據自己的需要,直接閱讀你所關注的內容。主要內容包括:設計核心,關注嵌入核心和嵌入存儲器;系統集成和超大規模集成電路的設計問題;AC掃描、正常速度掃描和嵌入式可測試性設計;內建、自測試、含內存BIST、邏輯BIST及掃描BIST;虛擬測試套接字和隔離測試 ·重用設計,包括重用和隔離測試;用vsia和IEEE P1500標準處理測試問題。 書中穿插的整幅圖解直接來自作者的教學材

    標簽: 數字集成電路 嵌入式 內核

    上傳時間: 2013-04-24

    上傳用戶:sjb555

  • SOC驗證方法

    Prakash Rashinkar has over 15 years experience in system design and verificationof embedded systems for communication satellites, launch vehicles and spacecraftground systems, high-performance computing, switching, multimedia, and wirelessapplications. Prakash graduated with an MSEE from Regional Engineering College,Warangal, in India. He lead the team that was responsible for delivering themethodologies for SOC verification at Cadence Design Systems. Prakash is anactive member of the vsia Functional Verification DWG. He is currently Architectin the Vertical Markets and Design Environments Group at Cadence.

    標簽: SOC 驗證方法

    上傳時間: 2014-01-24

    上傳用戶:xinhaoshan2016

  • SOC驗證方法

    Prakash Rashinkar has over 15 years experience in system design and verificationof embedded systems for communication satellites, launch vehicles and spacecraftground systems, high-performance computing, switching, multimedia, and wirelessapplications. Prakash graduated with an MSEE from Regional Engineering College,Warangal, in India. He lead the team that was responsible for delivering themethodologies for SOC verification at Cadence Design Systems. Prakash is anactive member of the vsia Functional Verification DWG. He is currently Architectin the Vertical Markets and Design Environments Group at Cadence.

    標簽: SOC 驗證方法

    上傳時間: 2013-11-19

    上傳用戶:m62383408

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