MSP430-JTAG-Adapter:MSP430-JTAG doesn’t need external power supply, as MSP430 microcontrollers require only 3-5 mA while programming and all necessary power supply is taken from the LPT port.
標簽： MSP 430 microcontrollers JTAG-Adapter
上傳時間： 2013-12-25
上傳用戶：洛木卓
Expert Choice represents a significant contribution to the decision making process 工t assists a decision maker in solving complex problems involving many criteria and several courses of action . An Expert Choice solution to a problem reflects the expertise of the decision maker , not the computer . Behavioral scientists have spent many years studying the human mind and how it makes decisions . They have found that humans are influenced by their previous experiences and this causes them to have biases . Basic instincts , preferences and environmental factors also play key roles in how we analyze data and make decisions . There 15 way to remove these factors from human decision making , nor would we necessarily want to , but as the problems of our world become more and more complex , it 15 necessary for us to employ a framework to help make more logical and less biased decisions while still taking our feelings and intuition into consideration .
標簽： contribution significant represents decision
上傳時間： 2015-06-02
上傳用戶：gmh1314
min_Pascal語言的語法，其中<循環語句>改為 ::= do<語句> while<條件>。壓縮包中還包括5個測試用例。 另外，如要文檔，請給我郵件。
標簽： min_Pascal 語言
上傳時間： 2015-06-03
上傳用戶：qunquan
Single-layer neural networks can be trained using various learning algorithms. The best-known algorithms are the Adaline, Perceptron and Backpropagation algorithms for supervised learning. The first two are specific to single-layer neural networks while the third can be generalized to multi-layer perceptrons.
標簽： Single-layer algorithms best-known networks
上傳時間： 2015-06-17
上傳用戶：趙云興
The J2000 codec was written in an effort to produce the cleanest and simplest implementation possible of the JPEG-2000 standard. We have put a particular emphasis on good architecture design and code simplicity, while at the same time providing an implementation as complete and efficient as possible. The source code for the codec is freely available for anyone to study or even for use in commercial programs. We hope that our open development process and our focus on clean, straightforward code will help make the J2000 codec become a reference implementation of the JPEG-2000 standard
標簽： implementation cleanest simplest produce
上傳時間： 2015-07-03
上傳用戶：dengzb84
1. PL/0 語言介紹 ●PL/0 程序設計語言是一個較簡單的語言，它以賦值語句為基礎，構造概念有順序、條件和重復（循環）三種。PL/0 有子程序概念，包括過程定義（可以嵌套）與調用且有局部變量說明。PL/0語言編譯程序采用以語法分析為核心、一遍掃描的編譯方法。詞法分析和代碼生成作為獨立的子程序供語法分析程序調用。語法分析的同時，提供了出錯報告和出錯恢復的功能。在源程序沒有錯誤編譯通過的情況下，調用類PCODE解釋程序解釋執行生成的類PCODE代碼。 ●保留字(關鍵字)：所謂保留字是指在Pascal語言中具有特定的含義。標準Pascal語言中的保留字一共有35個，Turbo Pascal語言一共有51個。下面是Pascal語言的保留字：AND，ARRAY，BEGIN，CASE，CONST，DIV，DO，DOWNTO，ELSE，END，FILE，FOR，FUNTION，GOTO，IF，IN，LABEL，MOD，NIL，NOT，OF，OR，PACKED，PROCEDURE，PROGRAM，RECORD，REPEAT，SET，THEN，TO，TYPE，UNTIL，VAR，while，WITH，EXPORTS，SHR，STRING，ASM，OBJECT，UNIT，CONSTRUCTOR，IMPLEMENTATION，DESTRUCTOR，USES，INHERITED，INLINE，INTERFACE，LIBRARY，XOR，SHL
上傳時間： 2015-07-17
上傳用戶：zm7516678
his project was built and tested with WinAVR-20060125. Make sure the MCU target define in the Makefiles corresponds to the AVR you are using!! To build the code, just install WinAVR and run "make" from the console in echomaster and echoslave subdirs. "make program" will program the device if you have a AVRISP attached. Remember to set the AVR device to at least 8MHz. The AVR may use the programmable clock from MC1319x, just remember to check if the MC1319x and SPI communication is working FIRST! Otherwise you wont get any clock signal to the AVR and then you can t program it or reset the fuses! The MC1319x has default clock output of 32kHz so you will have to set your programmer to a very low frequency (<=32kHz/4) to be able to program it while it is running on that!
標簽： the 20060125 project WinAVR
上傳時間： 2014-10-10
上傳用戶：yan2267246
關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標簽： investigates implementing pipelines circuits
上傳時間： 2015-07-26
上傳用戶：CHINA526
Coriander is a GUI for controlling a Digital Camera (in the sense of the IIDC specs issued by the 1394 Trade Association [1]). Due to the properties of the IEEE1394 protocol, Coriander can control an IEEE1394 camera without interferring with the image flow from that camera. It can thus be used to setup a camera with Coriander while the video flow is used by another application
標簽： the controlling Coriander Digital
上傳時間： 2015-08-07
上傳用戶：TF2015
一個基于網格和最近鄰居的聚類算法 Similarity(x, y) = size ( SKNN(x) SKNN(y) )，while Link(x, y)=1
標簽： SKNN Similarity size 網格
上傳時間： 2014-01-14
上傳用戶：zhangliming420
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