Control systems are used to regulate an enormous variety of machines, products, and processes. They control quantities such as motion, temperature, heat flow, fluid flow, fluid pressure, tension, voltage, and current. Most concepts in control theory are based on having sensors to measure the quantity under control. In fact, control theory is often taught assuming the availability of near-perfect feedback signals. Unfortunately, such an assumption is often invalid. Physical sensors have shortcomings that can degrade a control system.
標簽： Observers Control Systems in
上傳時間： 2020-06-10
上傳用戶：shancjb
An Arduino core for the ATmega328, ATmega168, ATmega88, ATmega48 and ATmega8, all running a [custom version of Optiboot for increased functionality](#write-to-own-flash). This core requires at least Arduino IDE v1.6.2, where v1.8.5+ is recommended. <br/> **This core gives you two extra IO pins if you're using the internal oscillator!** PB6 and PB7 is mapped to [Arduino pin 20 and 21](#pinout).<br/> If you're into "generic" AVR programming, I'm happy to tell you that all relevant keywords are being highlighted by the IDE through a separate keywords file. Make sure to test the [example files](https://github.com/MCUdude/MiniCore/tree/master/avr/libraries/AVR_examples/examples) (File > Examples > AVR C code examples). Try writing a register name, <i>DDRB</i> for instance, and see for yourself!
標簽： MiniCore
上傳時間： 2021-02-22
上傳用戶：
歐母龍PLC例程PLC控制器源碼255個合集:1600T俄羅斯壓力機.rar200噸壓機程序 omron 的機子C系列的.rar3MK136舊磨床現程序.rar3電機延時控制啟停.rar5V編碼器信號如何接入CP1H高數計數案例.rar6路搶答器源碼.rar902002 OMRON.rarASCII Generic Protocol Macro Object Code.zipASCII Generic Protocol Macro.zipC3電樞異物吸引.rarCalendar Calculation.zipcarbon.rarCompact Flash Memory Write.zipCounter Multiplex.zipcp1h 高速計數觸發中斷注意點.rarcp1h-x40用在非標飲料線上的程序,有注解.rarCP1H與愛默生溫控模塊的通訊程序.rarCP1L and CP1H EasyModbus FB.zipCPM1A編寫的贊揚15T立式注塑機.rarCPM2A Interupt High Speed Counting Sample.zipCPM2A自身時鐘六個時間段觸發程序.rarCQM1 Host Link Master.zipCQM1H 21的例子程序，有溫度壓力等PID控制。.rarCQMaster.swp.zipCS CJ CP NSJ password set.zipCS1 C Mode Hostlink.zipCS1-CJ1 Floating Point to Fixed Point Conversion for HMI.zipcub.rarCX-Programmer Ver.5 Introduction Guide R120-E1-01..zipCX-Programmer Ver.5 Introduction to Function Blocks Guide R121-E1-01.zipC_Mode_Hostlink.zipDeviceNet Explicit Message Example.zipdieban.rarEasy to use Modbus RTU Master for CP1L CP1H CJ1 CJ2 CS1.zipExample of Using Daylight Saving FB's.zipExample Scale Meter Protocol.zipFB Calculate Day Of Week.zipFB Day light savings function block.zipFB Extract Time Date into SecMin Hr Day Mth Yr.zipFB Scale with parameters.zipGKF1250離心機CXP.rargkf1250離心機cxpgkf離心機omron.rarJH21-200程序.rarLED液壓機.rarlogging+ filewrite.ziplpr-des.rarModbus Protocol Macro Object Code.zipModbus Protocol Macro.zipModbus RTU Sample Code CJ1-SCB.rarModbus TCP Client using FB's.zipOmron CS1 Sequencer.zipOMRON E6CP絕對值編碼器使用實例。編碼器為8位格雷碼輸出.rarOmron Modbus Slave Ladder.zipOmron Plc 變頻一帶三例程.rarOMRON PLC編程示范.raromron--MOV傳送指令.raromron-cs1g-h-cpu42日本機的程序.rarOmron_CJ2_to_AB_EIP_Tag_Datalink_Example.rarOMRON接駁臺.rarOMRON控制2伺服.rarOMRON溫度，壓力模擬量輸入程序.rarOMRON照明設備程序.raromron的PLC案例程序.rarOMRON程序舉例.rarOMRON程序舉例2.rarOMRON紙病分析系統-PLC程序(CJ1G).zipomron脈沖輸出到驅動器的程序.rarPCB 沉銅線程序.rarPID溫度控制的PLC程序設計實例.rarPinstamp.zipPLC Clock adjustment with screen.zipPLC錳鋼程序cpm2a.zipPolls and Writes setpoints to E5CK Process Controller - E5CK.swp.zipPRO9連拉.rarProcess states sequence logics.zipQuadrature Input for Standard CPM1A DC Inputs.zipRandom Number Generator.zipScaling in CJ1 CS1 PLC's.zipSMS - GSM PLC Communications.zipsony 公司 某機臺控制程序.rarStepNext.cpt.zipSTUP Example.zipTemplate for Step-Step Next Sequence.zipToggle Button.zipTracking product on conveyor.zipTXD-RXD Quickstart Programs.zipTXD-RXD Serial Port Handling.zipUseable timer.zipV600-E5CK.zipV700-V720 RFID Protocol Macro.zipVB與OMRON PLC通訊源碼.rarWoodwood Controler Example Protocol Program.zipYH32-315油壓機程序.rar一個CJ1M的程序.rar一個OMRON程序,帶位置控制模塊.rar一個生產線上潤滑控制的小程序.rar一些簡單的cpm1a程序.rar一控三恒壓供水程序.rar三層提升機歐姆龍CQM1H程序.rar三菱400噸和200號沖床程序.rar上海產自動模切機飛達部程序.zip上海獅印全自動啤機程序.rar東芝壓鑄機梯形圖.rar兩步法吹瓶機.rar鄉林剪臺.rar買書的隨書樣例.rar井研磨邊機.rar交通燈注釋全.rar今機立式注塑機程序.rar伺服電機正反轉控制.rar位置控制（旋轉編碼器與PLC）.rar充磁機程序.rar先啟后停 后啟先停 事例.rar沖床程序.rar分揀線主機一個CJ1M的分揀線程序下掛CP1H.rar利慧利樂灌裝機程序.rar刮水器停止位置檢查程序.rar力泰翻胚機程序.rar北人04印刷機程序.rar北人LQD10騎馬裝訂程序.rar半自動吹瓶機的程.rar南京印刷機.zip卡板程式.rar壓制機程序（帶解釋，注釋）.rar壓力機控制程序.rar原創液壓機程序帶注釋歐姆龍PLC加信捷文本.rar原點搜索程序.rar雙翻分揀機.rar雙邊機.rar反滲透整套PLC控制.rar臺灣產染色機歐姆龍PLC帶3只IO擴展控制程序.rar臺灣大拉無板.rar啤酒廠酒瓶美容機.rar四川綿陽建豐熱磨工段.rar在用設備程序.rar垂直涂布.rar外端子設計數值.rar大型熱電廠 PLC程序(帶注解).rar大搖動超聲波清洗機.rar大連75密練注釋程序.rar安呼12級.rar富佳扶梯程序.rar對齊度編程！！.rar小車控制程序.rar小車送料”例程.rar廣東鍛壓氣壓沖床程序（80T）有詳細注解.rar廣告牌燈箱.rar微電機刷簧自動組裝程序.rar微粉磚自動送料帶OMRON CQM2A+擴展程序帶注釋.rar意大利進口皮革壓花.rar扎鋼機程序.rar打包機.rar拔蓋機.rar撥碼控制.rar擋磚磨邊機（新1）.rar捷豹空壓機控制程序.rar接木機.rar控制程序例子.rar推掛.rar攻絲機2（新）.rar料位顯示.rar旋轉門控制程序1.rar無協議.rar無心磨床(OMRON系統,帶機械手有詳細注解).rar無線膠裝機歐姆龍程序.zip日本人編的程序 拋光研磨.rar日本成型磨床控制程序（附注釋）歐姆龍CPM1A.rar板坯定厚.rar樣例，有注釋.rar模擬量試驗.rar歐姆龍CJ1M鉻化機程序帶注釋.rar歐姆龍CP1H例程.rar歐姆龍CPM1A的PLC.rar歐姆龍CPM2AH PLC和歐姆龍NTZ觸摸屏編寫的超聲波清洗機程序..rar歐姆龍CPM2AH Host Link通訊程序(發布源碼).rar
上傳時間： 2021-10-22
上傳用戶：
FPGA讀寫SD卡讀取BMP圖片通過LCD顯示例程實驗 Verilog邏輯源碼Quartus工程文件+文檔說明,FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 實驗簡介在前面的實驗中我們練習了 SD 卡讀寫，VGA 視頻顯示等例程，本實驗將 SD 卡里的 BMP 圖片讀出，寫入到外部存儲器，再通過 VGA、LCD 等顯示。本實驗如果通過液晶屏顯示，需要有液晶屏模塊。2 實驗原理在前面的實驗中我們在 VGA、LCD 上顯示的是彩條，是 FPGA 內部產生的數據，本實驗將彩條替換為 SD 內的 BMP 圖片數據，但是 SD 卡讀取速度遠遠不能滿足顯示速度的要求，只能先寫入外部高速 RAM，再讀出后給視頻時序模塊顯示module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24
標簽： fpga
上傳時間： 2021-10-27
上傳用戶：
FPGA讀取OV5640攝像頭數據并通過VGA或LCD屏顯示輸出的Verilog邏輯源碼Quartus工程文件+文檔說明，FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上傳時間： 2021-12-18
上傳用戶：
基于FPGA設計的sdram讀寫測試實驗Verilog邏輯源碼Quartus工程文件+文檔說明，DRAM選用海力士公司的 HY57V2562 型號,容量為的 256Mbit,采用了 54 引腳的TSOP 封裝, 數據寬度都為 16 位, 工作電壓為 3.3V,并丏采用同步接口方式所有的信號都是時鐘信號。FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
標簽： fpga sdram verilog quartus
上傳時間： 2021-12-18
上傳用戶：
1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34
標簽： DDR4
上傳時間： 2022-01-09
上傳用戶：
Extensively rewritten to present the C++11 language, standard library, and key design techniques as an integrated whole, Stroustrup thoroughly addresses changes that make C++11 feel like a whole new language, offering definitive guidance for leveraging its improvements in performance, reliability, and clarity. C++ programmers around the world recognize Bjarne Stoustrup as the go-to expert for the absolutely authoritative and exceptionally useful information they need to write outstanding C++ programs. Now, as C++11 compilers arrive and development organizations migrate to the new standard, they know exactly where to turn once more: Stoustrup's C++ Programming Language, Fourth Edition.Bjarne Stroustrup是C++的設計師和最早的實現者，也是《C++程序設計語言》、《帶標注的C++參考手冊》和《C++語言的設計與演化》的作者。他從丹麥Aarhus大學和英國牛津大學畢業，現在是AT&T大規模程序設計研究部的負責人，AT&T特別成員，AT&T貝爾實驗室特別成員，以及ACM特別成員。Stroustrup的研究興趣包括分布式系統、操作系統、模擬、設計和程序設計。他也是Addison·Wesley的C++In-Depth系列書籍的編輯。
標簽： C++
上傳時間： 2022-02-01
上傳用戶：
verilog實現I2C通信的slave模塊源碼狀態機設位計可做I2C接口的仿真模型//`timescale 1ns/1psmodule I2C_slv (input [6:0] slv_id,input RESET,input scl_i, //I2C clkinput sda_i, //I2C data ininput [7:0] I2C_RDDATA,////////////////////////output reg sda_o, //I2C data outoutput reg reg_w, //reg write enable pulse (1T of scl_i)output reg [7:0] I2C_ADDR,output reg [7:0] I2C_DATA); parameter ST_ADDR = 4'd0; parameter ST_ACK = 4'd1; parameter ST_WDATA1 = 4'd2; parameter ST_WACK1 = 4'd3; parameter ST_WDATA2 = 4'd4; parameter ST_WACK2 = 4'd5; parameter ST_WDATA3 = 4'd6; parameter ST_WACK3 = 4'd7; parameter ST_RDATA1 = 4'd8; parameter ST_RACK1 = 4'd9; parameter ST_IDLE = 4'd15;//---------------------------------------------------------------------------// Signal Declaration//--------------------------------------------------------------------------- reg i2c_start_n, i2c_stop_n; //wire RESET_scl; wire i2c_stp_n, i2c_RESET; reg [3:0] i2c_cs, i2c_ns; reg [3:0] cnt_bit; reg [7:0] d_vec; reg i2c_rd, i2c_ack; reg [7:0] I2C_RDDATA_latch;
上傳時間： 2022-02-03
上傳用戶：
針對嵌入式產品程序更新問題,提出了一種基于IAP技術的STM32單片機在線固件升級方案,設計了STM32單片機最小系統硬件電路和USB轉串口通信電路,并給出了Bootloader程序、APP程序、PC上機程序的實現流程.實驗結果表明,該方案具有簡單實用、穩定性高、維護成本低和設備使用效率高的特點,適用于嵌入式產品升級.For the problem of updating embedded products program,an online firmware upgrade scheme of STM32 single chip microcomputer based on IAP technology is proposed.This scheme not only elaborates the principle of IAP technology in detail but also provides the design of the minimum system hardware circuit of STM32 MCU,the design of USB for serial communication circuit,and the implementation flow of Bootloader program,APP program and PC program.The experiment results show that the scheme is simple,practical and highly stable.In addition,it can be used to actual embedded product upgrading,significantly reducing maintenance costs and improving the efficiency of equipment.
上傳時間： 2022-03-25
上傳用戶：
