FPGA 具有輕松集成與支持新協(xié)議和新標(biāo)準(zhǔn)以及產(chǎn)品定制的能力，同時仍然可以實(shí)現(xiàn)快速的產(chǎn)品面市時間。在互聯(lián)網(wǎng)和全球市場環(huán)境中，外包制造變得越來越普遍，這使得安全變得更加重要。正如業(yè)界領(lǐng)袖出版的文章所述，反向工程、克隆、過度構(gòu)建以及篡改已經(jīng)成為主要的安全問題。據(jù)專家估計，每年因?yàn)榧倜爱a(chǎn)品而造成的經(jīng)濟(jì)損失達(dá)數(shù)十億美元。國際反盜版聯(lián)盟表示，這些假冒產(chǎn)品威脅經(jīng)濟(jì)的發(fā)展，并且給全球的消費(fèi)類市場帶來重大影響。本白皮書將確定設(shè)計安全所面臨的主要威脅，探討高級安全選擇，并且介紹xilinx 的新型、低成本SpartanTM-3A、Spartan-3AN 和Spartan-3A DSP FPGA 如何協(xié)助保護(hù)您的產(chǎn)品和利潤。
標(biāo)簽： Spartan FPGA 267 DSP
上傳時間： 2013-10-26
上傳用戶：simonpeng
Applying power to a standard logic chip, SRAM, or EPROM, usually results in output pinstracking the applied voltage as it rises. Programmable logic attempts to emulate that behavior,but physics forbids perfect emulation, due to the device programmability. It requires care tospecify the pin behavior, because programmable parts encounter unknown variables – yourdesign and your power environment.
標(biāo)簽： xilinx XAPP CPLD 440
上傳時間： 2013-11-24
上傳用戶：253189838
Design techniques for electronic systems areconstantly changing. In industries at the heart of thedigital revolution, this change is especially acute.Functional integration, dramatic increases incomplexity, new standards and protocols, costconstraints, and increased time-to-market pressureshave bolstered both the design challenges and theopportunities to develop modern electronic systems.One trend driving these changes is the increasedintegration of core logic with previously discretefunctions to achieve higher performance and morecompact board designs.
標(biāo)簽： System xilinx FPGA 151
上傳時間： 2013-11-23
上傳用戶：kangqiaoyibie
xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of xilinx. xilinx expressly disclaims any liability arising out of your use of the Documentation. xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
標(biāo)簽： Virtex FPGA PCB 設(shè)計手冊
上傳時間： 2013-11-11
上傳用戶：zwei41
The CoolRunner-II CPLD is a highly uniform family of fast, low-power devices. Theunderlying architecture is a traditional CPLD architecture, combining macrocells intofunction blocks interconnected with a global routing matrix, the xilinx AdvancedInterconnect Matrix (AIM). The function blocks use a PLA configuration that allowsall product terms to be routed and shared among any of the macrocells of the functionblock.
上傳時間： 2013-11-03
上傳用戶：1037540470
According to CIBC World Markets, Equity Research, theFlat Panel Display (FPD) industry has achieved sufficientcritical mass for its growth to explode. Thus, it can nowattract the right blend of capital investments and R&Dresources to drive technical innovation toward continuousimprovement in view quality, manufacturing efficiency,and system integration. These in turn are sustainingconsumer interest, penetration, revenue growth, and thepotential for increasing long-term profitability for industryparticipants. CIBC believes that three essential conditionsare now converging to drive the market forward
上傳時間： 2015-01-02
上傳用戶：小楓殘?jiān)?/p>
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時間： 2013-11-23
上傳用戶：shen_dafa
XAPP520將符合2.5V和3.3V I/O標(biāo)準(zhǔn)的7系列FPGA高性能I/O Bank進(jìn)行連接 The I/Os in xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
上傳時間： 2013-11-06
上傳用戶：wentianyou
一些應(yīng)用利用 xilinx FPGA 在每次啟動時可改變配置的能力，根據(jù)所需來改變 FPGA 的功能。xilinx Platform Flash XCFxxP PROM 的設(shè)計修訂 (Design Revisioning) 功能，允許用戶在單個PROM 中將多種配置存儲為不同的修訂版本，從而簡化了 FPGA 配置更改。在 FPGA 內(nèi)部加入少量的邏輯，用戶就能在 PROM 中存儲的多達(dá)四個不同的修訂版本之間進(jìn)行動態(tài)切換。多重啟動或從多個設(shè)計修訂進(jìn)行動態(tài)重新配置的能力，與 Spartan™-3E FPGA 和第三方并行 flashPROM 一起使用時所提供的 MultiBoot 選項(xiàng)相似。本應(yīng)用指南將進(jìn)一步說明 Platform Flash PROM 如何提供附加選項(xiàng)來增強(qiáng)配置失敗時的安全性，以及如何減少引腳數(shù)量和板面積。此外，Platform Flash PROM 還為用戶提供其他優(yōu)勢：iMPACT 編程支持、單一供應(yīng)商解決方案、低成本板設(shè)計和更快速的配置加載。本應(yīng)用指南還詳細(xì)地介紹了一個包含 VHDL 源代碼的參考設(shè)計。
標(biāo)簽： Platform Flash XAPP PROM
上傳時間： 2013-10-10
上傳用戶：wangcehnglin
WP369可擴(kuò)展式處理平臺-各種嵌入式系統(tǒng)的理想解決方案 ：Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,xilinx's architecture for a new Extensible Processing Platform is optimized for system power, cost, and size. Based on ARM's dual-core Cortex™-A9 MPCore processors and xilinx’s 28 nm programmable logic,the Extensible Processing Platform takes a processor-centric approach by defining a comprehensive processor system implemented with standard design methods. This approach provides Software Developers a familiar programming environment within an optimized, full featured,powerful, yet low-cost, low-power processing platform.
標(biāo)簽： 369 WP 擴(kuò)展式 處理平臺
上傳時間： 2013-10-18
上傳用戶：cursor
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