University Banking system
資源簡(jiǎn)介:University Banking system
上傳時(shí)間: 2014-01-22
上傳用戶:chfanjiang
資源簡(jiǎn)介:just do Banking system to see what is good or bad
上傳時(shí)間: 2013-12-23
上傳用戶:xinzhch
資源簡(jiǎn)介:internet Banking system
上傳時(shí)間: 2013-12-21
上傳用戶:shinesyh
資源簡(jiǎn)介:For about Banking system. I copy from CodeProject.com.
上傳時(shí)間: 2014-11-18
上傳用戶:啊颯颯大師的
資源簡(jiǎn)介:飛機(jī)訂票系統(tǒng),實(shí)現(xiàn)訂票,退票,查詢 the Banking system relates to multi-threaded, socket programming, and Singleton design pattern. Notes for the complete source Gilmour, documentation, together with the development process
上傳時(shí)間: 2016-04-02
上傳用戶:ma1301115706
資源簡(jiǎn)介:Programming Embedded system. Michael Point University of Leicester.
上傳時(shí)間: 2017-08-13
上傳用戶:refent
資源簡(jiǎn)介:bank apploication about banling system ..online Banking syastem
上傳時(shí)間: 2017-09-28
上傳用戶:牛津鞋
資源簡(jiǎn)介:FreeTTS is a speech synthesis system written entirely in the Java programming language. It is based upon Flite, a small, fast, run-time speech synthesis engine, which in turn is based upon University of Edinburgh s Festival Speech Synthe...
上傳時(shí)間: 2014-08-29
上傳用戶:cylnpy
資源簡(jiǎn)介:This a very simple baseband simulator for SC-FDMA system. This simulator is part of the upcoming book “Single Carrier FDMA: A New Air Interface for Long Term Evolution” (Wiley, Nov. 2008) which I co-authored with professor David J. Goodma...
上傳時(shí)間: 2016-08-26
上傳用戶:小草123
資源簡(jiǎn)介:A UML Documentation for an Elevator system:This paper is a PhD project report for the course Distributed Embedded systems at Carnegie Mellon University. Throughout this course, a distributed real-time system – an elevator control system–...
上傳時(shí)間: 2013-12-14
上傳用戶:zhouli
資源簡(jiǎn)介:this procedure is simulated document management system disk space management, Disk Management, directory management (single-level directory) of a simulation program, as well as University computer courses on operating system design a case, ...
上傳時(shí)間: 2017-02-05
上傳用戶:zhuoying119
資源簡(jiǎn)介:Analysis and Simulation of UHF RFID system Jin Li, Cheng Tao Modern Telecommunication Institute, Beijing Jiaotong University, Beijing 100044, P. R. China Abstract This article presents the analysis and simulation of UHF RFID system
上傳時(shí)間: 2013-12-21
上傳用戶:從此走出陰霾
資源簡(jiǎn)介:Embedded system Design: A Unified Hardware/Software Approach Frank Vahid and Tony Givargis Department of Computer Science and Engineering University of California
上傳時(shí)間: 2017-08-13
上傳用戶:wang5829
資源簡(jiǎn)介:system Generator 8.1。用戶將很快發(fā)現(xiàn)新版本帶來的全新感覺。新版本中大大增強(qiáng)了Block Dialog Boxes的功能,許多模塊的參數(shù)選擇功能也得到了加強(qiáng)。
上傳時(shí)間: 2013-07-09
上傳用戶:heminhao
資源簡(jiǎn)介:資料->【E】光盤論文->【E1】斯坦福博士論文->03 calgary PhD Improving the Inertial Navigation system (INS) Error Model for INS and INSDGPS Applications.pdf
上傳時(shí)間: 2013-08-01
上傳用戶:wzr0701
資源簡(jiǎn)介:This brief introduce a kind of the framework construction to materialize the system. And an example was given with the discussion on the performence.
上傳時(shí)間: 2013-08-17
上傳用戶:ysystc699
資源簡(jiǎn)介:Building a RISC system in an FPGA
上傳時(shí)間: 2013-09-04
上傳用戶:朗朗乾坤
資源簡(jiǎn)介:本設(shè)計(jì)的基本要求是以復(fù)雜可編程邏輯器件CPLD為基礎(chǔ),通過在EDA系統(tǒng)軟件ispDesignExpert system 環(huán)境下進(jìn)行數(shù)字系統(tǒng)設(shè)計(jì),熟練掌握該環(huán)境下的功能仿真,時(shí)間仿真,管腳鎖定和芯片下載。 本系統(tǒng)基本上比較全面的模擬了計(jì)數(shù)式數(shù)字頻率計(jì),廣泛應(yīng)用于工業(yè)、民用...
上傳時(shí)間: 2013-09-05
上傳用戶:文993
資源簡(jiǎn)介:system will automatically delete the directory
上傳時(shí)間: 2013-09-09
上傳用戶:toyoad
資源簡(jiǎn)介:? 本文簡(jiǎn)單討論并總結(jié)了VHDL、Verilog,system verilog 這三中語(yǔ)言的各自特點(diǎn)和區(qū)別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which la...
上傳時(shí)間: 2013-10-16
上傳用戶:牛布牛
資源簡(jiǎn)介:Introduce High-Speed Digital system Design.
上傳時(shí)間: 2013-10-20
上傳用戶:gps6888
資源簡(jiǎn)介:Xilinx公司推出的DSP設(shè)計(jì)開發(fā)工具system Generator是在Matlab環(huán)境中進(jìn)行建模,是DSP高層系統(tǒng)設(shè)計(jì)與Xilinx FPGA之間實(shí)現(xiàn)的“橋梁”。在分析了FPGA傳統(tǒng)級(jí)設(shè)計(jì)方法的基礎(chǔ)上,提出了基于system Generator的系統(tǒng)級(jí)設(shè)計(jì)新方法,并應(yīng)用新方法設(shè)計(jì)驗(yàn)證了一套數(shù)字下變...
上傳時(shí)間: 2013-11-18
上傳用戶:小草123
資源簡(jiǎn)介:匯編器在微處理器的驗(yàn)證和應(yīng)用中舉足輕重,如何設(shè)計(jì)通用的匯編器一直是研究的熱點(diǎn)之一。本文提出了一種開放式的匯編器系統(tǒng)設(shè)計(jì)思想,在匯編語(yǔ)言與機(jī)器語(yǔ)言間插入中間代碼CMDL(code mapping description language)語(yǔ)言,打破匯編語(yǔ)言與機(jī)器語(yǔ)言的直接映射關(guān)...
上傳時(shí)間: 2013-10-10
上傳用戶:meiguiweishi
資源簡(jiǎn)介:本文依據(jù)集成電路設(shè)計(jì)方法學(xué),探討了一種基于標(biāo)準(zhǔn)Intel 8086 微處理器的單芯片計(jì)算機(jī)平臺(tái)的架構(gòu)。研究了其與SDRAM,8255 并行接口等外圍IP 的集成,并在對(duì)AMBA協(xié)議和8086 CPU分析的基礎(chǔ)上,采用遵從AMBA傳輸協(xié)議的系統(tǒng)總線代替?zhèn)鹘y(tǒng)的8086 CPU三總線結(jié)構(gòu),搭建...
上傳時(shí)間: 2013-12-27
上傳用戶:kernor
資源簡(jiǎn)介:提出了一個(gè)由AT89C52單片機(jī)控制步進(jìn)電機(jī)的實(shí)例。可以通過鍵盤輸入相關(guān)數(shù)據(jù), 并根據(jù)需要, 實(shí)時(shí)對(duì)步進(jìn)電機(jī)工作方式進(jìn)行設(shè)置, 具有實(shí)時(shí)性和交互性的特點(diǎn)。該系統(tǒng)可應(yīng)用于步進(jìn)電機(jī)控制的大多數(shù)場(chǎng)合。實(shí)踐表明, 系統(tǒng)性能優(yōu)于傳統(tǒng)的步進(jìn)電機(jī)控制器。關(guān)鍵詞: 單片機(jī);...
上傳時(shí)間: 2013-11-19
上傳用戶:leesuper
資源簡(jiǎn)介:針對(duì)運(yùn)行中火車測(cè)速運(yùn)用多普勒效應(yīng)采用DSP 設(shè)計(jì)雷達(dá)測(cè)速系統(tǒng)并闡述了其基本設(shè)計(jì)思想與工作原理給出系統(tǒng)硬件軟件設(shè)計(jì)結(jié)構(gòu)和原理圖改善了原有光電測(cè)速精度提高了系統(tǒng)工作穩(wěn)定性和可靠性經(jīng)實(shí)驗(yàn)證明DSP 采集板工作穩(wěn)定測(cè)速效果好關(guān)鍵詞DSP; 雷達(dá)測(cè)速; 多普勒效應(yīng) ...
上傳時(shí)間: 2013-10-27
上傳用戶:003030
資源簡(jiǎn)介:The Linux Programming Interface - A Linux and UNIX system
上傳時(shí)間: 2013-11-10
上傳用戶:asdstation
資源簡(jiǎn)介:ARM embeded system designer,周立功版本,國(guó)內(nèi)較有名的一版。
上傳時(shí)間: 2013-10-31
上傳用戶:zaizaibang
資源簡(jiǎn)介: 完整性高的FPGA-PCB系統(tǒng)化協(xié)同設(shè)計(jì)工具 Cadence OrCAD and Allegro FPGA system Planner便可滿足較復(fù)雜的設(shè)計(jì)及在設(shè)計(jì)初級(jí)產(chǎn)生最佳的I/O引腳規(guī)劃,并可透過FSP做系統(tǒng)化的設(shè)計(jì)規(guī)劃,同時(shí)整合logic、schematic、PCB同步規(guī)劃單個(gè)或多個(gè)FPGA pin的最佳...
上傳時(shí)間: 2013-11-06
上傳用戶:wwwe
資源簡(jiǎn)介: 完整性高的FPGA-PCB系統(tǒng)化協(xié)同設(shè)計(jì)工具 Cadence OrCAD and Allegro FPGA system Planner便可滿足較復(fù)雜的設(shè)計(jì)及在設(shè)計(jì)初級(jí)產(chǎn)生最佳的I/O引腳規(guī)劃,并可透過FSP做系統(tǒng)化的設(shè)計(jì)規(guī)劃,同時(shí)整合logic、schematic、PCB同步規(guī)劃單個(gè)或多個(gè)FPGA pin的最佳...
上傳時(shí)間: 2013-10-19
上傳用戶:shaojie2080