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The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlledby the I2C-bus. The low ON-state resistance of the switch allows connections to be madewith minimal propagation delay. Any individual A to B channel or combination of channelscan be selected via the I2C-bus, determined by the contents of the programmable Controlregister. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow fromPort A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open,creating a high-impedance state between the two ports, which stops the data flow.An ACTIVE LOW reset input (RESET) allows the PCA9549 to recover from a situationwhere the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-busstate machine and causes all the bits to be open, as does the internal power-on resetfunction.
標(biāo)簽：
switch
Octal
9549
with
上傳時間：
2014-11-22
上傳用戶：xcy122677
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The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallelInput/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed toenhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvementsinclude higher drive capability, 5 V I/O tolerance, lower supply current, individual I/Oconfiguration, and smaller packaging. I/O expanders provide a simple solution whenadditional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.The PCA9555 consists of two 8-bit Configuration (Input or Output selection); Input, Outputand Polarity Inversion (ACTIVE HIGH or ACTIVE LOW operation) registers. The systemmaster can enable the I/Os as either inputs or outputs by writing to the I/O configurationbits. The data for each Input or Output is kept in the corresponding Input or Outputregister. The polarity of the read register can be inverted with the Polarity Inversionregister. All registers can be read by the system master. Although pin-to-pin and I2C-busaddress compatible with the PCF8575, software changes are required due to theenhancements, and are discussed in Application Note AN469.
標(biāo)簽：
C-bus
9555
SMBu
PCA
上傳時間：
2013-11-13
上傳用戶：fredguo
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The PCA9548A is an octal bidirectional translating switch controlled via the I2C-bus. TheSCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individualSCx/SDx channel or combination of channels can be selected, determined by thecontents of the programmable control register.An ACTIVE LOW reset input allows the PCA9548A to recover from a situation where one ofthe downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets theI2C-bus state machine and causes all the channels to be deselected as does the internalPower-on reset function.
標(biāo)簽：
channel
9548A
9548
PCA
上傳時間：
2013-10-13
上傳用戶：bakdesec
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The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for
SMBus and I2C-bus applications. The PCA9557 consists of an 8-bit input port register,
8-bit output port register, and an I2C-bus/SMBus interface. It has low current consumption
and a high-impedance open-drain output pin, IO0.
The system master can enable the PCA9557’s I/O as either input or output by writing to
the configuration register. The system master can also invert the PCA9557 inputs by
writing to the ACTIVE HIGH polarity inversion register. Finally, the system master can reset
the PCA9557 in the event of a time-out by asserting a LOW in the reset input.
The power-on reset puts the registers in their default state and initializes the
I2C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to
occur without de-powering the part.
標(biāo)簽：
C-bus
SMBus
reset
port
上傳時間：
2014-01-18
上傳用戶：bs2005
-
The MAX3243E device consists of three line drivers, five line receivers, and a dual charge-pump circuit with±15-kV ESD (HBM and IEC61000-4-2, Air-Gap Discharge) and ±8-kV ESD (IEC61000-4-2, Contact Discharge)protection on serial-port connection pins. The device meets the requirements of TIA/EIA-232-F and provides theelectrical interface between an asynchronous communication controller and the serial-port connector. Thiscombination of drivers and receivers matches that needed for the typical serial port used in an IBM PC/AT, orcompatible. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-Vsupply. In addition, the device includes an always-ACTIVE noninverting output (ROUT2B), which allowsapplications using the ring indicator to transmit data while the device is powered down. The device operates atdata signaling rates up to 250 kbit/s and a maximum of 30-V/ms driver output slew rate.
標(biāo)簽：
MULTICHANNEL
5.5
TO
RS
上傳時間：
2013-10-19
上傳用戶：ddddddd
-
The Philips family of Multiplexers and Switches consists of bi-directional translating switches controlled via the I2C or SMBus to fan out an upstream SCL/SDA pair to 2, 4 or 8 downstream channels of SCx/SDx pairs. The Multiplexers allow only one downstream channel to be selected at a time, while the Switches allow any individual downstream channel or combination of downstream channels to be selected, depending on the content of the programmable control register. Once one or several channels have been selected, the device acts as a wire, allowing the master on the upstream channel to send commands to devices on all the ACTIVE downstream channels, and devices on the ACTIVE downstream channels to communicate with each other and the master. External pull-up resistors are used to pull each individual channel up to the desired voltage level. Combined interrupt output and hardware reset input are device options that are featured.
標(biāo)簽：
SMBus
954X
PCA
954
上傳時間：
2013-10-11
上傳用戶：dianxin61
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本文簡單介紹了MCGS 組態(tài)軟件和SPCE061A 單片機的特點，即北京昆侖通態(tài)自動化軟件科技有限公司的工控組態(tài)軟件MCGS(Monitor and Control Generated System )和臺灣凌陽科技推出的16 位微控制器SPCE061A，重點介紹了如何一步步開發(fā)SPCE061A 單片機的驅(qū)動程序，并簡單介紹了下位機程序的設(shè)計，最后給出了測試情況。計算機技術(shù)的飛速發(fā)展為工業(yè)自動化開辟了廣闊的發(fā)展空間，人們可以快捷地開發(fā)和組建高效的控制系統(tǒng)。筆者設(shè)計的液體點滴監(jiān)控模型,可以對液體點滴情況實現(xiàn)遠(yuǎn)程監(jiān)控和現(xiàn)場監(jiān)控，終端和上位機均可人工設(shè)定所需的液體點滴速度并動態(tài)顯示。在這方面，MCGS 工控組態(tài)軟件提供了強有力的支持，它是一套Windows 環(huán)境下快速構(gòu)造和生成上位機監(jiān)控系統(tǒng)的組態(tài)軟件系統(tǒng)，可快速構(gòu)造和生成數(shù)據(jù)采集、報警處理、流程控制、動畫顯示、報表輸出等界面,實現(xiàn)各種工程曲線的繪制、報表輸出、遠(yuǎn)程通信等功能 [1]。MCGS 作為一種方便有效的通用工控軟件,它提供了國內(nèi)外各種常用的工控設(shè)備的驅(qū)動程序。但在實際應(yīng)用中,因為所用設(shè)備的特殊性,允許用戶根據(jù)需要來定制設(shè)備驅(qū)動程序。MCGS 用ACTIVE DLL 構(gòu)件實現(xiàn)設(shè)備驅(qū)動程序,通過規(guī)范的OLE 接口掛接到MCGS 中,使其構(gòu)成一個整體。鑒于Visual Basic 語言的通用性和簡單性,使用VB 來開發(fā)單片機驅(qū)動,MCGS 的實現(xiàn)方法和原理與標(biāo)準(zhǔn)的ACTIVE DLL 完全一致,但MCGS 規(guī)定了一套接口規(guī)范,只有遵守這些接口規(guī)范的ACTIVE DLL 才能用作MCGS 的設(shè)備驅(qū)動構(gòu)件。利用具有語音和 DSP 功能的SPCE061A 單片機作為液體點滴監(jiān)控模型的核心控制器，SPCE061A 是臺灣凌陽科技推出的16 位微控制器，提供了豐富的軟、硬件資源，開發(fā)靈活方便。除此之外SPCE061A 的最高時鐘頻率可達(dá)到49MHz,具有運算速度高的優(yōu)勢，這為語音的錄制和播放提供了條件[4]。
標(biāo)簽：
MCGS
凌陽單片機
驅(qū)動程序
上傳時間：
2013-12-19
上傳用戶：leesuper
-
Prakash Rashinkar has over 15 years experience in system design and verificationof embedded systems for communication satellites, launch vehicles and spacecraftground systems, high-performance computing, switching, multimedia, and wirelessapplications. Prakash graduated with an MSEE from Regional Engineering College,Warangal, in India. He lead the team that was responsible for delivering themethodologies for SOC verification at Cadence Design Systems. Prakash is anACTIVE member of the VSIA Functional Verification DWG. He is currently Architectin the Vertical Markets and Design Environments Group at Cadence.
標(biāo)簽：
SOC
驗證方法
上傳時間：
2014-01-24
上傳用戶：xinhaoshan2016
-
This example provides a description of how to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sends the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must end by '\r'character (keypad ENTER button). Each byte received is retransmitted to theHyperterminal. The string that you have entered is stored in the RxBuffer array. The receivebuffer have a RxBufferSize bytes as maximum.
The USART2 is configured as follow: - BaudRate = 115200 baud - Word Length = 8 Bits - One Stop Bit - No parity - Hardware flow control enabled (RTS and CTS signals) - Receive and transmit enabled - USART Clock disabled - USART CPOL: Clock is ACTIVE low - USART CPHA: Data is captured on the second edge - USART LastBit: The clock pulse of the last data bit is not output to the SCLK pin
標(biāo)簽：
V100
STM
100
32V
上傳時間：
2013-10-31
上傳用戶：yy_cn
-
Prakash Rashinkar has over 15 years experience in system design and verificationof embedded systems for communication satellites, launch vehicles and spacecraftground systems, high-performance computing, switching, multimedia, and wirelessapplications. Prakash graduated with an MSEE from Regional Engineering College,Warangal, in India. He lead the team that was responsible for delivering themethodologies for SOC verification at Cadence Design Systems. Prakash is anACTIVE member of the VSIA Functional Verification DWG. He is currently Architectin the Vertical Markets and Design Environments Group at Cadence.
標(biāo)簽：
SOC
驗證方法
上傳時間：
2013-11-19
上傳用戶：m62383408
