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Bench

這是rs（255

這是rs（255，223）編碼的verilog源程序。里面有：encode、decode、test－Bench等文件。

標(biāo)簽： 255

上傳時(shí)間： 2015-07-18

上傳用戶：wendy15
encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in

encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplication inverse of an Galois field element test-Bench.v The test fixture, and some brief notes on using the modules. data-rom.v A simple data source for testing run For those intelligence-challenged who can t run verilog LGPL The license

標(biāo)簽： Berlekamp berlekamp algorithm generator

上傳時(shí)間： 2014-02-16

上傳用戶：fxf126@126.com
HDL實(shí)現(xiàn)的DES算法

HDL實(shí)現(xiàn)的DES算法，及相關(guān)的Test Bench激勵(lì)文件

標(biāo)簽： HDL DES 算法

上傳時(shí)間： 2015-09-21

上傳用戶：sk5201314
The Hardware folder contains the following files:- 1) Sram_Interface.bit -----------------> Bi

The Hardware folder contains the following files:- 1) Sram_Interface.bit -----------------> Bitstream File 2) Sram_Interface.ucf -----------------> UCF File 3) Sram_Interface.vhd -----------------> Main Entity 4) Sram_Interface_tb.vhd ------------> Test Bench 5) SRAM_RD_WR.vhd ------------> Sub Module

標(biāo)簽： Sram_Interface following Hardware contains

上傳時(shí)間： 2014-11-11

上傳用戶：gmh1314
This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDR

This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test Bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec

標(biāo)簽： Development Startix2 tailored Altera

上傳時(shí)間： 2014-01-19

上傳用戶：chongcongying
基于 xinlinx 寫的DES加密算法

基于 xinlinx 寫的DES加密算法，內(nèi)涵test Bench，加密解密都有

標(biāo)簽： xinlinx DES 加密算法

上傳時(shí)間： 2016-01-04

上傳用戶：dreamboy36
計(jì)數(shù)器鎖存器 12位寄存器帶load

計(jì)數(shù)器鎖存器 12位寄存器帶load，clr等功能的寄存器雙向腳（clocked bidirectional pin）一個(gè)簡單的狀態(tài)機(jī) 一個(gè)同步狀態(tài)機(jī) 用狀態(tài)機(jī)設(shè)計(jì)的交通燈控制器數(shù)據(jù)接口一個(gè)簡單的UART 測試向量（Test Bench）舉例：加法器源程序相應(yīng)加法器的測試向量test Bench）

標(biāo)簽： load 計(jì)數(shù)器位寄存器鎖存器

上傳時(shí)間： 2014-01-16

上傳用戶：bjgaofei
作為數(shù)字集成電路的硬件工程師

作為數(shù)字集成電路的硬件工程師，在做設(shè)計(jì)的時(shí)候，寫Test Bench是很重要的，甚至重要過你的一些設(shè)計(jì)本身，因?yàn)樗梢源_定你的設(shè)計(jì)是否可用可行，并且能夠優(yōu)化你的設(shè)計(jì)。

標(biāo)簽： 數(shù)字集成電路硬件工程師

上傳時(shí)間： 2014-01-01

上傳用戶：ggwz258
The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontro

The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontroller. It is not, and is not intended as, a high fidelity circuit simulation. This package includes the following files. Note that the license agreement is stated in the main VHDL file, PICCPU.VHD and common questions are answered in the file SYNTHPIC.TXT Files: README.TXT This file.. SYNTHPIC.TXT Questions and Answers PICCPU.VHD Main processor VHDL file PICALU.VHD ALU for the PICCPU PICREGS.VHD Data memory PICROM.VHD Program memory (created by HEX2VHDL utility) PICTEST.VHD Simple test Bench I used to do testing (optional) PICTEST.CMD My Viewlogic ViewSim command file (again, optional) TEST1.ASM First program I assembled and ran on it. TEST2.ASM Another test program.. TEST3.ASM Yet another.. TEST4.ASM Yet another.. TEST5.ASM Yet another.. TEST6.ASM Yet another.. HEX2VHDL.CPP Utility for converting

標(biāo)簽： synthesizable microcontro Synthetic PIC

上傳時(shí)間： 2013-12-22

上傳用戶：妄想演繹師
Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuff

Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check for bit unstuffing errors]. Otherwise complete and fully functional. There is currently no test Bench available. This core is very simple and is proven in hardware. I see no point of writing a test Bench at this time.

標(biāo)簽： conversion Includes parallel stuffing

上傳時(shí)間： 2017-03-11

上傳用戶：hn891122