■ High Performance, Low Power AVR? 8-Bit Microcontroller ■ Advanced RISC Architecture –120 Powerful Instructions – Most Single CLOCK Cycle Execution –32 x 8 General Purpose Working Registers –Fully Static Operation
標簽： Atmel
上傳時間： 2013-06-01
上傳用戶：tccc
比例-積分-微分（PID）是過程控制中最常用的一種控制算法。算法簡單而且容易理解，應用十分廣泛。但由于應用領域的不同，功能上差別很大，系統的控制要求及關心的控制對象也不相同。數字PID控制比連續PID控制更為優越，因為計算機程序的靈活性，很容易克服連續PID控制中存在的問題，經修正而得到更完善的數字PID算法。本文以三相全控整流橋阻性負載為實際電路，控制主電路電壓，旨在提出一種智能數字PID控制系統的設計思路，并給出了詳細的硬件設計及初步軟件設計思路。 PID控制系統采用高性能、低功耗的ARM微處理器S3C44BO作為核心處理單元，內部的10位ADC作為信號采集模塊，采用了矩陣鍵盤和640*480的液晶作為人機接口；串口作為通信模塊實現了上位機的監控。采用芯片內部自帶的PWM模塊，輸出16M Hz PWM信號并經過一階低通濾波器得到0～5V的控制信號用于觸發主電路控制器，實現PID整定。 軟件方面，分析和研究了uC/OSⅡ的內核源碼，實現了其在32位微處理器上的移植，作為管理各個子程序執行的系統軟件。選用了圖形處理軟件uC/GUI用于完成LCD顯示及控制。PID算法采用了增量式數字PID算法，采用規一化算法進行參數選取。上位機部分采用了C＃語言進行編寫。另外，采用了RTC（Real Time CLOCK）作為系統時鐘，可以實現系統的定時運行、定時模式切換等。在上位機上也可以方便的控制程序的執行，實現遠程監控。 在論文的最后詳細的介紹了智能PID控制系統在三相全控橋主電路中的具體應用。總結了調試中遇到的問題，對今后工作中需要進一步改善和探索的地方進行了展望。
上傳時間： 2013-08-01
上傳用戶：lvzhr
BGA布線指南 BGA CHIP PLACEMENT AND ROUTING RULE BGA是PCB上常用的組件，通常CPU、NORTH BRIDGE、SOUTH BRIDGE、AGP CHIP、CARD BUS CHIP…等，大多是以bga的型式包裝，簡言之，80﹪的高頻信號及特殊信號將會由這類型的package內拉出。因此，如何處理BGA package的走線，對重要信號會有很大的影響。 通常環繞在BGA附近的小零件，依重要性為優先級可分為幾類： 1. by pass。 2. CLOCK終端RC電路。 3. damping（以串接電阻、排組型式出現；例如memory BUS信號） 4. EMI RC電路（以dampin、C、pull height型式出現；例如USB信號）。 5. 其它特殊電路（依不同的CHIP所加的特殊電路；例如CPU的感溫電路）。 6. 40mil以下小電源電路組（以C、L、R等型式出現；此種電路常出現在AGP CHIP or含AGP功能之CHIP附近，透過R、L分隔出不同的電源組）。 7. pull low R、C。 8. 一般小電路組（以R、C、Q、U等型式出現；無走線要求）。 9. pull height R、RP。 中文DOC，共5頁，圖文并茂
上傳時間： 2013-04-24
上傳用戶：cxy9698
This application note is intended for system designers who require a hardware implementation overview of the development board features such as the power supply, the CLOCK management, the reset control, the boot mode settings and the debug management. It shows how to use the High-density and Medium-density STM32F10xxx product families and describes the minimum hardware resources required to develop an STM32F10xxx application.
上傳時間： 2013-04-24
上傳用戶：epson850
英文描述： Synchronous Up/Down Decade Counters(single CLOCK line) 中文描述： 同步向上/向下十年計數器（單時鐘線）
上傳時間： 2013-06-18
上傳用戶：haohaoxuexi
Abstract: This application note describes how sampling CLOCK jitter (time interval error or "TIE jitter") affectsthe performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately specifying low-frequency (< 2x passband frequency) and high-frequency or wideband (> 2xpassband frequency) jitter tolerance in these devices. The article also provides an application example ofa simple highly jittered cycle-skipped sampling CLOCK and describes a method for generating a properbroadband jittered CLOCK. The document then goes on to compare Maxim's audio DAC jitter tolerance tocompetitor audio DACs. Maxim's exceptionally high jitter tolerance allows very simple and low-cost sampleCLOCK implementations.
上傳時間： 2013-10-25
上傳用戶：banyou
With more and more multi-frequency CLOCKs being used in today's chips, especially in the communications field, it is often necessary to switch the source of a CLOCK line while the chip is running.
上傳時間： 2013-10-10
上傳用戶：1214209695
Many applications require a CLOCK signal to be synchronous, phase-locked, or derived fromanother signal, such as a data signal or another CLOCK. This type of CLOCK circuit is important in
上傳時間： 2014-12-23
上傳用戶：qq21508895
Most circuit designers are familiar with diode dynamiccharacteristics such as charge storage, voltage dependentcapacitance and reverse recovery time. Less commonlyacknowledged and manufacturer specifi ed is diode forwardturn-on time. This parameter describes the timerequired for a diode to turn on and clamp at its forwardvoltage drop. Historically, this extremely short time, unitsof nanoseconds, has been so small that user and vendoralike have essentially ignored it. It is rarely discussed andalmost never specifi ed. Recently, switching regulator CLOCKrate and transition time have become faster, making diodeturn-on time a critical issue. Increased CLOCK rates aremandated to achieve smaller magnetics size; decreasedtransition times somewhat aid overall effi ciency but areprincipally needed to minimize IC heat rise. At CLOCK speedsbeyond about 1MHz, transition time losses are the primarysource of die heating.
上傳時間： 2013-10-10
上傳用戶：誰偷了我的麥兜
A complete design for a data acquisition card for the IBM PC is detailed in this application note. Additionally, C language code is provided to allow sampling of data at speed of more than 20kHz. The speed limitation is strictly based on the execution speed of the "C" data acquisition loop. A "Turbo" XT can acquire data at speeds greater than 20kHz. Machines with 80286 and 80386 processors can go faster than 20kHz. The computer that was used as a test bed in this application was an XT running at 4.77MHz and therefore all system timing and acquisition time measurements are based on a 4.77MHz CLOCK speed.
上傳時間： 2013-10-29
上傳用戶：BOBOniu
