The PCA9517 is a CMOS integrated circuit that provides level shifting between lowvoltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the CLOCK (SCL) lines, thus enabling two buses of 400 pF. Usingthe PCA9517 enables the system designer to isolate two halves of a bus for both voltageand capacitance. The SDA and SCL pins are over voltage tolerant and arehigh-impedance when the PCA9517 is unpowered.
標(biāo)簽： translating Level 9517 PCA
上傳時(shí)間： 2013-12-25
上傳用戶：wsf950131
The PCA9518 is a BiCMOS integrated circuit intended forapplication in I2C and SMBus systems.While retaining all the operating modes and features of the I2Csystem, it permits extension of the I2C-bus by buffering both thedata (SDA) and the CLOCK (SCL) lines, thus enabling virtuallyunlimited buses of 400 pF.
標(biāo)簽： Expandable 5channel 9518 PCA
上傳時(shí)間： 2013-10-23
上傳用戶：dumplin9
The PCA9519 is a 4-channel level translating I2C-bus/SMBus repeater that enables theprocessor low voltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the CLOCK (SCL) lines, thus enabling the I2C-bus or SMBusmaximum capacitance of 400 pF on the higher voltage side. The SDA and SCL pins areover-voltage tolerant and are high-impedance when the PCA9519 is unpowered.
標(biāo)簽： 4channel transla level 9519
上傳時(shí)間： 2013-11-19
上傳用戶：jisiwole
The main oscillator allows either a crystal or single-ended input CLOCK signal. Cost-sensitiveapplications typically use an external crystal with the on-chip oscillator circuit since it is the mostcost-effective solution. It is also possible to use the internal oscillator to CLOCK the device after theboot process has completed.
標(biāo)簽： Stellaris CLOCKing Options for
上傳時(shí)間： 2013-10-14
上傳用戶：pol123
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, CLOCK inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the CLOCK cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU CLOCK. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
標(biāo)簽： Signal Input Fall Rise
上傳時(shí)間： 2013-10-23
上傳用戶：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, CLOCK inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the CLOCK cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU CLOCK. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
標(biāo)簽： C16x 微控制器 輸入信號 時(shí)序圖
上傳時(shí)間： 2014-04-02
上傳用戶：han_zh
當(dāng)拿到一張CASE單時(shí)，首先得確定的是能用什么母體才能實(shí)現(xiàn)此功能，然后才能展開對外圍硬件電路的設(shè)計(jì)，因此首先得了解每個(gè)母體的基本功能及特點(diǎn)，下面大至的介紹一下本公司常用的IC：單芯片解決方案• SN8P1900 系列– 高精度 16-Bit 模數(shù)轉(zhuǎn)換器– 可編程運(yùn)算放大器 (PGIA)• 信號放大低漂移: 2V• 放大倍數(shù)可編程: 1/16/64/128 倍– 升壓- 穩(wěn)壓調(diào)節(jié)器 (Charge-Pump Regulator)• 電源輸入: 2.4V ~ 5V• 穩(wěn)壓輸出: e.g. 3.8V at SN8P1909– 內(nèi)置液晶驅(qū)動電路 (LCD Driver)– 單芯片解決方案 • 耳溫槍 SN8P1909 LQFP 80 Pins• 5000 解析度量測器 SN8P1908 LQFP 64 Pins• 體重計(jì) SN8P1907 SSOP 48 Pins單芯片解決方案• SN8P1820 系列– 精確的12-Bit 模數(shù)轉(zhuǎn)換器– 可編程運(yùn)算放大器 (PGIA)• Gain Stage One: Low Offset 5V, Gain: 16/32/64/128• Gain Stage One: Low Offset 2mV, Gain: 1.3 ~ 2.5– 升壓- 穩(wěn)壓調(diào)節(jié)器• 電源輸入: 2.4V ~ 5V• 穩(wěn)壓輸出: e.g. 3.8V at SN8P1829– 內(nèi)置可編程運(yùn)算放大電路– 內(nèi)置液晶驅(qū)動電路 – 單芯片解決方案 • 電子醫(yī)療器 SN8P1829 LQFP 80 Pins 高速/低功耗/高可靠性微控制器• 最新SN8P2000 系列– SN8P2500/2600/2700 系列– 高度抗交流雜訊能力• 標(biāo)準(zhǔn)瞬間電壓脈沖群測試 (EFT): IEC 1000-4-4• 雜訊直接灌入芯片電源輸入端• 只需添加1顆 2.2F/50V 旁路電容• 測試指標(biāo)穩(wěn)超 4000V (歐規(guī))– 高可靠性復(fù)位電路保證系統(tǒng)正常運(yùn)行• 支持外部復(fù)位和內(nèi)部上電復(fù)位• 內(nèi)置1.8V 低電壓偵測可靠復(fù)位電路• 內(nèi)置看門狗計(jì)時(shí)器保證程序跳飛可靠復(fù)位– 高抗靜電/栓鎖效應(yīng)能力– 芯片工作溫度有所提高: -200C ~ 700C 工規(guī)芯片溫度： -400C ~ 850C 高速/低功耗/高可靠性微控制器• 最新 SN8P2000 系列– SN8P2500/2600/2700 系列– 1T 精簡指令級結(jié)構(gòu)• 1T: 一個(gè)外部振蕩周期執(zhí)行一條指令• 工作速度可達(dá)16 MIPS / 16 MHz Crystal– 工作消耗電流 < 2mA at 1-MIPS/5V– 睡眠模式下消耗電流 < 1A / 5V額外功能• 高速脈寬調(diào)制輸出 (PWM)– 8-Bit PWM up to 23 KHz at 12 MHz System CLOCK– 6-Bit PWM up to 93 KHz at 12 MHz System CLOCK– 4-Bit PWM up to 375 KHz at 12 MHz System CLOCK• 內(nèi)置高速16 MHz RC振蕩器 (SN8P2501A)• 電壓變化喚醒功能• 可編程控制沿觸發(fā)/中斷功能– 上升沿 / 下降沿 / 雙沿觸發(fā)• 串行編程接口
標(biāo)簽： 單片機(jī) 線路設(shè)計(jì)
上傳時(shí)間： 2013-10-21
上傳用戶：jiahao131
用單片機(jī)配置FPGA—PLD設(shè)計(jì)技巧 Configuration/Program Method for Altera Device Configure the FLEX Device You can use any Micro-Controller to configure the FLEX device–the main idea is CLOCKing in ONE BITof configuration data per CLOCK–start from the BIT 0The total Configuration time–e.g. 10K10 need 15K byte configuration file•calculation equation–10K10* 1.5= 15Kbyte–configuration time for the file itself•15*1024*8*CLOCK = 122,880CLOCK•assume the CLOCK is 4MHz•122,880*1/4Mhz=30.72msec
標(biāo)簽： FPGA PLD 用單片機(jī) 設(shè)計(jì)技巧
上傳時(shí)間： 2013-10-09
上傳用戶：a67818601
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system CLOCKs, reducing CLOCK skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-13
上傳用戶：瓦力瓦力hong
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback CLOCK. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output CLOCK can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上傳時(shí)間： 2013-10-15
上傳用戶：euroford
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