<li id="iq26m"></li> This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board ControlLER can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
上傳時間： 2013-11-01
上傳用戶：wojiaohs
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a ControlLER that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上傳時間： 2014-11-26
上傳用戶：erkuizhang
The PLB BRAM Interface ControlLER is a module thatattaches to the PLB (Processor Local Bus).
上傳時間： 2013-10-27
上傳用戶：Breathe0125
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing ControlLER (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-23
上傳用戶：shen_dafa
教學提示：可編程序控制器(Programmable Logic ControlLER,簡稱PLC)是以微處理器為核心，綜合計算機技術、自動控制技術和通信技術發展起來的一種新型工業自動控制裝置。隨著大規模、超大規模集成電路技術和數字通信技術的進步和發展，PLC技術不斷提高，在工業生產中獲得極其廣泛的應用。教學要求：本章讓學生了解PLC及其控制系統的基本知識，重點了解PLC的技術特點、類型以及發展概況。第一章 可編程序控制器概論1.1 PLC的定義及特點1.1.1 PLC的產生及定義1.1.2 PLC的特點1.1.3 PLC的分類1.2 PLC的發展趨勢
標簽： 可編程序控制器
上傳時間： 2013-10-28
上傳用戶：bnfm
ref-sdr-sdram-vhdl代碼 SDR SDRAM ControlLER v1.1 readme.txt This readme file for the SDR SDRAM ControlLER includes information that was not incorporated into the SDR SDRAM ControlLER White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.
上傳時間： 2013-10-23
上傳用戶：半熟1994
a8259 可編程中斷控制 altera提供 The a8259 is designed to simplify the implementation of the interrupt interface in 8088 and 8086 based microcomputer systems. The device is known as a programmable interrupt ControlLER. The a8259 receives and prioritizes up to 8 interrupts, and in the cascade mode, this can be expanded up to 64 interrupts. An asynchronous reset and a clock input have been added to improve operation and reliability.
上傳時間： 2015-01-02
上傳用戶：panpanpan
The power of programmability gives industrial automation designers a highly efficient， cost-effective alternative to traditional motor control units （MCUs）。 The parallel-processing power， fast computational speeds， and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control algorithms such as Field Oriented Control （FOC）。 Additionally， Xilinx devices lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing （DSP） that can tackle compute-intensive functions such as PID ControlLER， Clark/Park transforms， and Space Vector PWM. The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving， proven， motor-control reference designs. The kit also shortens the process of developing custom control capabilities， with integrated peripheral functions （Ethernet， PowerLink， and PCI® Express）， a motor-control FPGA mezzanine card （FMC） with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators， and prototyping support for evaluating alternative front-end circuitry.
上傳時間： 2013-10-28
上傳用戶：wujijunshi
CAN（ControlLER Area Network——控制器局域網）是一種由 CAN 控制器組成的高性能串行數據局域通信網絡，是國際上應用最廣泛的現場總線之一。它最早由德國 Bosch 公司于 1984 年推出，最初用于汽車內部測量與執行部件之間的數據通信。CAN-bus 總線模型符合 OSI 的 7 層結構；CAN-bus 規范已被 ISO 估計標準組織制定為國際標準。
上傳時間： 2013-11-13
上傳用戶：lvzhr
Abstract: This application note explains how to design an intelligent lighting ControlLER that senses and measures the ambient lightlevel with an ambient light sensor (ALS). Equipped with a real-time clock (RTC), the ControlLER also knows when to turn lighting on oroff at specified times. The system presented in this document can be used to control all luminaires that are mains-supply operated.ControlLER software is also provided in hex format.
上傳時間： 2013-11-18
上傳用戶：AbuGe
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