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Designing withProgrammable Logicin an Analog WorldProgrammable logic DEVICESrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-logic density DEVICES that usenonvolatile sea-of-gates cells calledcomplex programmable logic DEVICES(CPLDs) or they can be high-densityDEVICES based on SRAM look-up tables
標(biāo)簽：
Solutions
Analog
Xilinx
FPGAs
上傳時間：
2013-11-07
上傳用戶：suicone
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This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash DEVICES) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.
標(biāo)簽：
XAPP
PROM
694
讀取
上傳時間：
2013-10-09
上傳用戶：guojin_0704
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This application note provides users with a general understanding of the SVF and XSVF fileformats as they apply to Xilinx DEVICES. Some familiarity with IEEE STD 1149.1 (JTAG) isassumed. For information on using Serial Vector Format (SVF) and Xilinx Serial Vector Format(XSVF) files in embedded programming applications
標(biāo)簽：
Xilinx
XAPP
XSVF
503
上傳時間：
2015-01-02
上傳用戶：時代將軍
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Most designers wish to utilize as much of a device as possible in order to enhance the overallproduct performance, or extend a feature set. As a design grows, inevitably it will exceed thearchitectural limitations of the device. Exactly why a design does not fit can sometimes bedifficult to determine. Programmable logic DEVICES can be configured in almost an infinitenumber of ways. The same design may fit when you use certain implementation switches, andfail to fit when using other switches. This application note attempts to clarify the CPLD softwareimplementation (CPLDFit) options, as well as discuss implementation tips in CoolRunnerTM-IIdesigns in order to maximize CPLD utilization.
標(biāo)簽：
XAPP
CPLD
444
配件
上傳時間：
2014-01-11
上傳用戶：a471778
-
This Application Note covers the basics of how to use Verilog as applied to ComplexProgrammable Logic DEVICES. Various combinational logic circuit examples, such asmultiplexers, decoders, encoders, comparators and adders are provided. Synchronous logiccircuit examples, such as counters and state machines are also provided.
標(biāo)簽：
Verilog
XAPP
CPLD
143
上傳時間：
2013-11-11
上傳用戶：y13567890
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This introduction covers the fundamentals of VHDL as applied to Complex ProgrammableLogic DEVICES (CPLDs). Specifically included are those design practices that translate soundlyto CPLDs, permitting designers to use the best features of this powerful language to extractoptimum performance for CPLD designs.
標(biāo)簽：
XAPP
CPLD
VHDL
105
上傳時間：
2013-11-21
上傳用戶：gtf1207
-
This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higherdensity DEVICES. To obtain the VHDL source code described in this document, go to sectionVHDL Code, page 5 for instructions.
標(biāo)簽：
CoolRunner-II
XAPP
CPLD
380
上傳時間：
2013-10-26
上傳用戶：kiklkook
-
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware DEVICES. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
標(biāo)簽：
Virtex
FPGA
PCB
設(shè)計手冊
上傳時間：
2013-11-11
上傳用戶：zwei41
-
The CoolRunner-II CPLD is a highly uniform family of fast, low-power DEVICES. Theunderlying architecture is a traditional CPLD architecture, combining macrocells intofunction blocks interconnected with a global routing matrix, the Xilinx AdvancedInterconnect Matrix (AIM). The function blocks use a PLA configuration that allowsall product terms to be routed and shared among any of the macrocells of the functionblock.
標(biāo)簽：
CPLD
264
WP
數(shù)字
上傳時間：
2013-11-03
上傳用戶：1037540470
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The introduction of Spartan-3™ DEVICES has createdmultiple changes in the evolution of embedded controldesigns and pushed processing capabilities to the “almostfreestage.” With these new FPGAs falling under $20, involume, with over 1 million system gates, and under $5for 100K gate-level units, any design with programmablelogic has a readily available 8- or 16-bit processor costingless than 75 cents and 32-bit processor for less than $1.50.
標(biāo)簽：
Spartan
FPGA
200
WP
上傳時間：
2013-10-21
上傳用戶：ligi201200
