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PK51是為8051系列單片機所設計的開發工具，支持所有8051系列衍生產品，，支持帶擴展存儲器和擴展指令集（例如Dallas390/5240/400,Philips 51MX,Analog DEVICES MicroConverters）的新設備,以及支持很多公司的一流的設備和IP內核,比如Analog DEVICES, Atmel, Cypress Semiconductor, Dallas Semiconductor, Goal, Hynix, Infineon, Intel, NXP(founded by Philips), OKI, Silicon Labs,SMSC, STMicroeleectronics,Synopsis, TDK, Temic, Texas Instruments,Winbond等。通過PK51專業級開發工具，可以輕松地了解8051的On-chip peripherals與及其它關鍵特性。
標簽：
8051
pk
51
上傳時間：
2013-10-09
上傳用戶：1109003457
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This overview guide describes all the peripherals available for TMS320x28xx and TMS320x28xxx DEVICES.Section 2 shows the peripherals used by each device. Section 3 provides descriptions of the peripherals.You can download the peripheral guide by clicking on the literature number, which is linked to the portable document format (pdf) file.
標簽：
281x
Dsp
281
外設
上傳時間：
2013-11-21
上傳用戶：HGH77P99
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中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger DEVICES one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly enhanced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽：
UltraScale
Xilinx
架構
上傳時間：
2013-11-13
上傳用戶：瓦力瓦力hong
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Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave DEVICES. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.
標簽：
PicoBlaze
Create
Master
Xilinx
上傳時間：
2013-11-05
上傳用戶：a6697238
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Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor DEVICES. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
標簽：
封裝
器件
用戶
賽靈思
上傳時間：
2013-10-22
上傳用戶：ztj182002
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Designing withProgrammable Logicin an Analog WorldProgrammable logic DEVICESrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-logic density DEVICES that usenonvolatile sea-of-gates cells calledcomplex programmable logic DEVICES(CPLDs) or they can be high-densityDEVICES based on SRAM look-up tables
標簽：
Solutions
Analog
Xilinx
FPGAs
上傳時間：
2013-11-01
上傳用戶：a67818601
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Designing withProgrammable Logicin an Analog WorldProgrammable logic DEVICES revolutionizeddigital design over 25 years ago,promising designers a blank chip todesign literally any function and programit in the field. PLDs can be low-logicdensity DEVICES that use nonvolatilesea-of-gates cells called complexprogrammable logic DEVICES (CPLDs)or they can be high-density DEVICESbased on SRAM look-up tables (LUTs)
標簽：
Solutions
Analog
Altera
FPGAs
上傳時間：
2013-11-08
上傳用戶：蟲蟲蟲蟲蟲蟲
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This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash DEVICES) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.
標簽：
XAPP
PROM
694
讀取
上傳時間：
2013-11-11
上傳用戶：zhouli
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This application note provides users with a general understanding of the SVF and XSVF fileformats as they apply to Xilinx DEVICES. Some familiarity with IEEE STD 1149.1 (JTAG) isassumed. For information on using Serial Vector Format (SVF) and Xilinx Serial Vector Format(XSVF) files in embedded programming applications
標簽：
Xilinx
XAPP
XSVF
503
上傳時間：
2013-10-21
上傳用戶：tiantwo
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Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware DEVICES. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
標簽：
Virtex
FPGA
PCB
設計手冊
上傳時間：
2014-01-13
上傳用戶：竺羽翎2222
