基于ti tms320c672x下音頻開發例子程式，包括eq Delay chorus等，還包括usb控制
上傳時間： 2016-07-28
上傳用戶：66666
NIST Net – A Linux-based Network Emulation Tool, It is a raw IP packet filter with many controllable channel parameters such as packet loss ratio, jitter, bandwidth variation, Delay, and network buffer size. To simulate different network environments
標簽： controllable Linux-based Emulation Network
上傳時間： 2014-01-26
上傳用戶：xauthu
一定要在TC下運行，需要包括一些頭文件，如graphic.h 要求：畫一輛小車不停地水平從屏幕左邊運動到右邊，隨著每一遍運動，小車高度均勻下降，降到最低后返回最高處 相關函數：Delay(),kbhit(),lineto(),moveto(),arc(),circle()等。
標簽： 運行
上傳時間： 2016-08-18
上傳用戶：彭玖華
VC++環境下的延時程序。sleep函數，還有Delay函數。
上傳時間： 2016-10-15
上傳用戶：685
This diskette (version 1.0) contains demonstration programs and source codes in MATLAB (v.5.2) for algorithms listed in the textbook Global Positioning Systems, Inertial Navigation, and Integration, by M. S. Grewal, Lawrence Weill, and A. P. Andrews, published by John Wiley and Sons, 2000. Contents: MATLAB (Version 5.2) Demonstrations & Scripts Chapter4 ephemeris.m calculates the GPS satellite position in ECEF coordinates from its ephemeris parameters. Chapter5 Klobuchar_fix.m calculates the ionospheric Delay. Chapter6 (shows the quaternion utilities)
標簽： demonstration diskette contains programs
上傳時間： 2016-10-20
上傳用戶：壞天使kk
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the Delay information (Tplh, Tphl) in your design.
上傳時間： 2013-12-13
上傳用戶：himbly
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the Delay information (Tplh, Tphl) in your design.
上傳時間： 2014-01-20
上傳用戶：三人用菜
DDR SDRAM控制器的VHDL源代碼，含詳細設計文檔。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上傳時間： 2014-11-01
上傳用戶：l254587896
A novel met hod t o p artially compensate sigma2delta shap ed noise is p rop osed. By injecting t he comp en2 sation cur rent int o t he p assive loop f ilte r during t he Delay time of t he p hase f requency detect or ( PFD) , a maximum reduction of t he p hase noise by about 16dB can be achieved. Comp a red t o ot he r compensation met hods , t he tech2 nique p rop osed he re is relatively simple and easy t o implement . Key building blocks f or realizing t he noise cancel2 lation , including t he Delay va riable PFD and comp ensation cur rent source , a re sp ecially designed. Bot h t he behavior level and circuit level simulation results a re p resented.
標簽： sigma2delta compensate injecting artially
上傳時間： 2013-12-18
上傳用戶：qlpqlq
Permits to negotiate of simple form (without code) some of the most utilized combinations of keys in the forms. It suffices with freeing the component on the form and to activate the properties desired segun the behavior that want. * ENTER to change of field. * ESC to close the form * to Advance al following control * to Delay al previous control * function Keys *.. .
標簽： combinations negotiate of utilized
上傳時間： 2014-01-15
上傳用戶：linlin
