The objective of this projectis to design, model and simulate an autocorrelation generator circuit using 4-bit LFSR. the register and LFSR will used D flip-flop and some gates. By the autocorrelation concept, there should be 2 same length vectors, for calculating the autocorrelation , we have to design the register for storing the original vector and the shifter for make time Delay.
標簽： autocorrelation objective generator projectis
上傳時間： 2015-08-17
上傳用戶：ikemada
數字選臺收音機 注意： （1）遙控發射芯片用TC9012/TC9243 經常用到的還有UPD6121和LC7461，它們的不同只處在于引導碼的時間不同或者數據位的個數不同，接受原理基本一樣。將本程序的相關位置修改就可以通用。 系統時鐘22.1184MHZ，如果用其他的時鐘請將Delay.c文件中的定時器裝載值修改一下 （2） 鍵盤檢測在VFD程序中，16312可以驅動VFD，另外外部可接24個按鍵，并將按鍵值放到 其內部的存儲中，使用時只須發命令讀即可。 （3） 由于時間原因，只給出調幅波段的自動搜臺功能，調頻的自動搜臺程序和調幅一樣，自己寫了。 （4）主要用在組合機和功放機上的收音頭大部分以LC72171做鎖象環，LA1823做高中頻處理 和音頻解調，但是有的數調收音頭把鎖象環和高頻處理做在一起，典型的有TEA5757和TEA5756 TEA5757采用了一種所謂的自動調諧系統，在自動搜索時無須讀中頻，簡化了程序。
上傳時間： 2013-12-28
上傳用戶：gxmm
oid led8_test(void) { int i, j, k iic_init() for( ) { for(j=0 j<10 j++) { for(i=0 i<8 i++) { k = 9-(i+j)％10 iic_write(0x70, 0x10+i, f_szDigital[k]) } Delay(1000) } } }
上傳時間： 2013-12-19
上傳用戶：BOBOniu
一個簡單的串口文件發送接受程序。可以調節發送延遲。里面的類可以應用在其他的環境下。A simple program that can send a file through a serial port. The Delay and other parameters are changable.
標簽： program through simple serial
上傳時間： 2014-01-22
上傳用戶：zsjinju
This simple program help you to calculate parameters for a pid controller for first order systems wiith Delay using different method: Ziegler Nichols,Cohen coon,IMC...
標簽： controller parameters calculate for
上傳時間： 2015-11-09
上傳用戶：yuanyuan123
Mobile phones are constantly decreasing in size, thereby complicating the acoustical functionality. Signal processing methods can be used to partially mitigate this problem. In this paper we suggest a method which uses multiple spectral subtraction functions and two microphones, introducing only a short signal Delay.
標簽： functionality complicating acoustical constantly
上傳時間： 2015-11-15
上傳用戶：youth25
This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct Delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
標簽： Development Startix2 tailored Altera
上傳時間： 2014-01-19
上傳用戶：chongcongying
The present paper deals with the problem of calculating mean Delays in polling systems with either exhaustive or gated service. We develop a mean value analysis (MVA) to compute these Delay figures. The merits of MVA are in its intrinsic simplicity and its intuitively appealing derivation. As a consequence, MVA may be applied, both in an exact and approximate manner, to a large variety of models.
標簽： with calculating present polling
上傳時間： 2014-11-17
上傳用戶：kelimu
This example streams input from a ADC source to a DAC. An analog signal is acquired block-by-block into SDRAM from the ADC (an AD9244 in this example). The frames are then output with a one-frame Delay to the DAC (an AD9744 in this example). In this example, no processing is done on the frames. They are passed unaltered.
標簽： block-by-block acquired example streams
上傳時間： 2015-12-29
上傳用戶：bjgaofei
名稱：read2543 功能：TLC2543驅動模塊 輸入參數：port通道號 輸出參數：ad轉換值 *************************************/ uint read2543(uchar port) { uint ad=0,i CLOCK=0 _CS=0 port<<=4 for(i=0 i<12 i++) { if(D_OUT) ad|=0x01 D_IN=(bit)(port&0x80) CLOCK=1 Delay(3) CLOCK=0 Delay(3) port<<=1 ad<<=1 } _CS=1 ad>>=1 return(ad) }
上傳時間： 2016-01-21
上傳用戶：R50974
