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Describes

1-Wire總線主機

Abstract: Communication with 1-Wire slave devices requires a 1-Wire master. There are numerous ways to build a 1-Wire master (see reference design 4206, "Choosing the Right 1-Wire Master for Embedded Applications"). Thisdocument Describes the DS1WM, a synthesizable 1-Wire master that can be implemented in an application-specificintegrated circuit (ASIC) or field-programmable gate array (FPGA).

標簽： Wire 總線主機

上傳時間： 2014-12-22

上傳用戶：xanxuan
MAXQ1050評估套件和面向MAXQ30入門的CrossStudio編譯

Abstract: This application note Describes how to create, build, and debug applications targeted for the MAXQ1050 RISC

標簽： MAXQ CrossStudio 1050 30

上傳時間： 2014-08-11

上傳用戶：qwerasdf
射頻和微波系統的建模與仿真

Abstract: This application note Describes system-level characterization and modeling techniques for radio frequency (RF) and microwavesubsystem components. It illustrates their use in a mixed-signal, mixed-mode system-level simulation. The simulation uses an RF transmitterwith digital predistortion (DPD) as an example system. Details of this complex system and performance data are presented.

標簽： 射頻仿真微波系統建模

上傳時間： 2013-12-18

上傳用戶：onewq
通過整合硬件分立收發器簡化AISG的控制系統

Abstract: This article Describes the Antenna Interface Standards Group (AISG) standard in telecommunications and details itshardware implementation. It explains how a fully integrated transceiver such as the MAX9947 can help reduce space and cost, andsolve bus arbitrations in base-station tower equipment.

標簽： AISG 硬件分立收發器控制系統

上傳時間： 2014-12-30

上傳用戶：wangchong
LPC1700系列芯片勘誤手冊

This errata sheet Describes both the known functional problems and anydeviations from the electrical specifications known at the release date ofthis document.Each deviation is assigned a number and its history is tracked in a table atthe end of the document.

標簽： 1700 LPC 系列芯片勘誤

上傳時間： 2013-11-22

上傳用戶：liangliang123
LPC1100系列微控制器勘誤手冊

This errata sheet Describes both the known functional problems and anydeviations from the electrical specifications known at the release date ofthis document.Each deviation is assigned a number and its history is tracked in a table atthe end of the document.

標簽： 1100 LPC 微控制器勘誤

上傳時間： 2014-12-31

上傳用戶：thuyenvinh
使用Nios II軟件構建工具

使用Nios II軟件構建工具 This chapter Describes the Nios® II Software Build Tools (SBT), a set of utilities and scripts that creates and builds embedded C/C++ application projects, user library projects, and board support packages (BSPs). The Nios II SBT supports a repeatable, scriptable, and archivable process for creating your software product. You can invoke the Nios II SBT through either of the following user interfaces: ■ The Eclipse™ GUI ■ The Nios II Command Shell The purpose of this chapter is to make you familiar with the internal functionality of the Nios II SBT, independent of the user interface employed.

標簽： Nios 軟件

上傳時間： 2013-10-12

上傳用戶：china97wan
Nios II 系列處理器配置選項

Nios II 系列處理器配置選項:This chapter Describes the Nios® II Processor parameter editor in Qsys and SOPC Builder. The Nios II Processor parameter editor allows you to specify the processor features for a particular Nios II hardware system. This chapter covers the features of the Nios II processor that you can configure with the Nios II Processor parameter editor; it is not a user guide for creating complete Nios II processor systems.

標簽： Nios II 列處理器

上傳時間： 2015-01-01

上傳用戶：mahone
AN522: Implementing Bus LVDS

This application note Describes how to implement the Bus LVDS (BLVDS) interface in the supported Altera ® device families for high-performance multipoint applications. This application note also shows the performance analysis of a multipoint application with the Cyclone III BLVDS example.

標簽： Implementing LVDS 522 Bus

上傳時間： 2013-10-26

上傳用戶：蘇蘇蘇蘇
XAPP694-從配置PROM讀取用戶數據

This application note Describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.

標簽： XAPP PROM 694 讀取

上傳時間： 2013-10-09

上傳用戶：guojin_0704