This application note Describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.
上傳時間： 2013-11-11
上傳用戶：zhouli
This application note Describes how the existing dual-port block memories in the Spartan™-IIand Virtex™ families can be used as Quad-Port memories. This essentially involves a dataaccess time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the blockmemory in terms of bits per second will remain the same.
上傳時間： 2013-11-08
上傳用戶：lou45566
This application note Describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上傳時間： 2013-10-15
上傳用戶：euroford
XAPP520將符合2.5V和3.3V I/O標準的7系列FPGA高性能I/O Bank進行連接 The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application note Describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
上傳時間： 2013-11-19
上傳用戶：yyyyyyyyyy
1 Communication Protocol (Computer as master) The communication protocol Describes here allows your computer to access 4096 internal registers (W0000-W4095) and 1024 internal relays (B0000-B1023) in the Workstation.. 1.1 Request Message Format Request message is a command message to be sent from the computer to the Workstation. The data structure of request message is shown below. Note that numbers are always in hexadecimal form and converted into ASCII characters. For example, Workstation unit number 14 will appear in the message as character 0(30h) followed by character E(45h); a BCC of 5Ah will appear in the message as character 5(35h) followed by character A(41h).
上傳時間： 2013-10-28
上傳用戶：cxl274287265
Abstract: Many industrial/scientific/medical (ISM) band radio frequency (RF) receivers use an external Sallen-Key datafilter and a data slicer to generate the baseband digital output. This tutorial Describes the ISM-RF Baseband Calculator,which can be used to calculate the filter capacitor values and the data slicer RC components, while providing a visualexample of the baseband signals.
上傳時間： 2013-11-04
上傳用戶：jkhjkh1982
This application note Describes a reference system which illustrates how to build an embeddedPowerPC® system using the Xilinx 1-Gigabit Ethernet Media Access Controller processor core.This system has the PLB_Gemac configured to use Scatter/Gather Direct Memory Access andthe Serializer/Deserializer (SerDes) interface. This application note Describes how to set up thespecific clocking structure required for the SerDes interface and the constraints to be added tothe UCF file. This reference system is complete with a standalone software application to testsome of the main features of this core, including access to registers, DMA capabilities, transmitand receive in loopback mode. This reference system is targeted for the ML300 evaluationboard.
上傳時間： 2013-11-01
上傳用戶：truth12
This article Describes the procedure to configure and program EXAR Corporation’s PowerXR Digital Power devicesvia I2C interface. Details shown here apply to XRP7704/08/40 and XRP7713/14 devices and PowerArchitectsoftware version 3.00.
上傳時間： 2013-10-20
上傳用戶：tianyi223
Abstract: This reference design provides design ideas for a cost-effective, low-power liquid-level measurement dataacquisition system (DAS) using a compensated silicon pressure sensor and a high-precision delta-sigma ADC. Thisdocument discusses how to select the compensated silicon pressure sensor, suggest system algorithms, and providenoise analyses. It also Describes calibration ideas to improve system performance while also reducing complexity andcost.
上傳時間： 2013-10-08
上傳用戶：sjy1991
The CodeWarrior Development Suite provides access and technical support to amultitude of CodeWarrior products. In this quick start guide, Section 1 explains howto register your CodeWarrior Development Suite. Section 2 explains how to activateand install one of your products. Section 3 Describes what you are entitled to withthe purchase of your CodeWarrior Development Suite, and Section 4 discusses theavailable purchase options. Section 5 Describes the benefits of maintaining a currenttechnical support contract, and Section 6 tells you how to access support.
標簽： CodeWarrior 開發套件
上傳時間： 2014-03-02
上傳用戶：784533221
