Testbenches have become an integral part of the design process, enabling you to verify that
your HDL model is sufficiently tested before implementing your design and helping you automate
the design verification process. It is essential, therefore, that you have confidence your
testbench is thoroughly exercising your design. Collecting code coverage statistics during simulation
helps to ensure the quality and thoroughness of your tests.
PCI設計指南The Xilinx LogiCORE PCI interface is a fully verified, pre-implemented
PCI Bus interface. This interface is available in 32-bit and 64-
bit versions, with support for multiple Xilinx FPGA device families. It
is designed to support both Verilog-HDL and VHDL. The design
examples in this book are provided in Verilog.
