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HdlC vhdl

  • HDLC協(xié)議RS485總線控制器的FPGA實(shí)現(xiàn)

    介紹了HDLC協(xié)議RS485總線控制器的FPGA實(shí)現(xiàn)

    標(biāo)簽: HDLC FPGA 485 RS

    上傳時(shí)間: 2013-10-18

    上傳用戶:zhengjian

  • 用FPGA實(shí)現(xiàn)RS485通信接口芯片

    在點(diǎn)對多點(diǎn)主從通信系統(tǒng)中,需要合適的接口形式和通信協(xié)議實(shí)現(xiàn)主站與各從站的信息交換。RS -485 接口是適合這種需求的一種標(biāo)準(zhǔn)接口形式。當(dāng)選擇主從多點(diǎn)同步通信方式時(shí),工作過程與幀格式符合HDLC/SDLC協(xié)議。介紹了采用VHDL 語言在FPGA 上實(shí)現(xiàn)的以HDLC/ SDLC 協(xié)議控制為基礎(chǔ)的RS - 485 通信接口芯片。實(shí)驗(yàn)表明,這種接口芯片操作簡單、體積小、功耗低、可靠性高,極具實(shí)用價(jià)值。

    標(biāo)簽: FPGA 485 RS 通信接口

    上傳時(shí)間: 2014-01-02

    上傳用戶:z240529971

  • The VHDL Cookbook (VHDL編碼書籍)

    The VHDL Cookbook是 是VHDL編碼書籍。

    標(biāo)簽: VHDL Cookbook The 編碼

    上傳時(shí)間: 2013-11-19

    上傳用戶:lixqiang

  • US Navy VHDL Modelling Guide

      This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.

    標(biāo)簽: Modelling Guide Navy VHDL

    上傳時(shí)間: 2013-11-20

    上傳用戶:pzw421125

  • PLD Programming Using VHDL

    本文詳細(xì)討論了VHDL語句對PLD設(shè)計(jì)的影響和設(shè)計(jì)經(jīng)驗(yàn),經(jīng)典文章,值得仔細(xì)閱讀消化。,PLD Programming Using VHDL

    標(biāo)簽: Programming Using VHDL PLD

    上傳時(shí)間: 2013-10-14

    上傳用戶:www240697738

  • VHDL,Verilog,System verilog比較

      本文簡單討論并總結(jié)了VHDL、Verilog,System verilog 這三中語言的各自特點(diǎn)和區(qū)別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.

    標(biāo)簽: Verilog verilog System VHDL

    上傳時(shí)間: 2014-03-03

    上傳用戶:zhtzht

  • 基于CPLD的VHDL語言數(shù)字鐘(含秒表)設(shè)計(jì)

    利用一塊芯片完成除時(shí)鐘源、按鍵、揚(yáng)聲器和顯示器(數(shù)碼管)之外的所有數(shù)字電路功能。所有數(shù)字邏輯功能都在CPLD器件上用VHDL語言實(shí)現(xiàn)。這樣設(shè)計(jì)具有體積小、設(shè)計(jì)周期短(設(shè)計(jì)過程中即可實(shí)現(xiàn)時(shí)序仿真)、調(diào)試方便、故障率低、修改升級容易等特點(diǎn)。 本設(shè)計(jì)采用自頂向下、混合輸入方式(原理圖輸入—頂層文件連接和VHDL語言輸入—各模塊程序設(shè)計(jì))實(shí)現(xiàn)數(shù)字鐘的設(shè)計(jì)、下載和調(diào)試。

    標(biāo)簽: CPLD VHDL 語言 數(shù)字

    上傳時(shí)間: 2013-10-24

    上傳用戶:古谷仁美

  • 基于FPGA的多通道HDLC通信系統(tǒng)設(shè)計(jì)與實(shí)現(xiàn)

    為了滿足某測控平臺(tái)的設(shè)計(jì)要求,設(shè)計(jì)并實(shí)現(xiàn)了基于FPGA的六通道HDLC并行通信系統(tǒng)。該系統(tǒng)以FPGA為核心,包括FPGA、DSP、485轉(zhuǎn)換接口等部分。給出了系統(tǒng)的電路設(shè)計(jì)、關(guān)鍵模塊及軟件流程圖。測試結(jié)果表明,系統(tǒng)通訊速度為1 Mb/s,并且工作穩(wěn)定,目前該設(shè)計(jì)已經(jīng)成功應(yīng)用于某樣機(jī)中。

    標(biāo)簽: FPGA HDLC 多通道 通信

    上傳時(shí)間: 2013-10-12

    上傳用戶:as275944189

  • ZBT SRAM控制器參考設(shè)計(jì),xilinx提供VHDL代碼

    ZBT SRAM控制器參考設(shè)計(jì),xilinx提供VHDL代碼 Description:   Contains the following files     readme.txt appnote_zbtp.vhd appnote_zbtf.vhd appnote_zbt.ucf Platform:   All Installation/Use:   Use 'unzip' on the .zip file and 'gunzip' followed by 'tar -xvf' on the .tar.gz file.

    標(biāo)簽: xilinx SRAM VHDL ZBT

    上傳時(shí)間: 2013-10-25

    上傳用戶:peterli123456

  • USB接口控制器參考設(shè)計(jì),xilinx提供VHDL代碼 us

    USB接口控制器參考設(shè)計(jì),xilinx提供VHDL代碼 usb xilinx vhdl ;  This program is free software; you can redistribute it and/or modify ;  it under the terms of the GNU General Public License as published by ;  the Free Software Foundation; either version 2 of the License, or ;  (at your option) any later version. ;      ;  This program is distributed in the hope that it will be useful, ;  but WITHOUT ANY WARRANTY; without even the implied warranty of ;  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the ;  GNU General Public License for more details. ;      ;  You should have received a copy of the GNU General Public License ;  along with this program; if not, write to the Free Software ;  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

    標(biāo)簽: xilinx VHDL USB us

    上傳時(shí)間: 2013-10-29

    上傳用戶:zhouchang199

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