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通過比較各種隔離數(shù)字通信的特點(diǎn)和應(yīng)用范圍，指出塑料光纖在隔離數(shù)字通信中的優(yōu)勢(shì)。使用已經(jīng)標(biāo)準(zhǔn)化的TOSLINK接口，有利于節(jié)省硬件開發(fā)成本和簡化設(shè)計(jì)難度。給出了塑料光纖的硬件驅(qū)動(dòng)電路，說明設(shè)計(jì)過程中的注意事項(xiàng)，對(duì)光收發(fā)模塊的電壓特性和頻率特性進(jìn)行全面試驗(yàn)，并給出SPI口使用塑料光纖隔離通信的典型應(yīng)用電路圖。試驗(yàn)結(jié)果表明，該設(shè)計(jì)可為電力現(xiàn)場、電力電子及儀器儀表的設(shè)計(jì)提供參考。 Abstract: y comparing characteristics and applications area of various isolated digital communications， this article indicates advantages of plastic optical fiber in isolated digital communications. Using the standardized TOSLINK interface， it helps to control costs and difficulty in hardware development and design. Then it gives the hardware driver circuit of plastic optical fiber module， explains the noticed details in design process， gives results on the basis of the optical transceiver module voltage characteristics and frequency characteristics tests. Finally，it gives typical application circuit of the SPI communication port by using plastic optical fiber isolation .The results show that this design can be referenced for the power field， power electronics and instrumentation design.
標(biāo)簽： 塑料光纖 高壓隔離 通信 接口設(shè)計(jì)
上傳時(shí)間： 2014-01-10
上傳用戶：gundan
Single-Ended and Differential S-Parameters Differential circuits have been important incommunication systems for many years. In the past,differential communication circuits operated at lowfrequencies, where they could be designed andanalyzed using lumped-element models andtechniques. With the frequency of operationincreasing beyond 1GHz, and above 1Gbps fordigital communications, this lumped-elementapproach is no longer valid, because the physicalsize of the circuit approaches the size of awavelength.Distributed models and analysis techniques are nowused instead of lumped-element techniques.Scattering parameters, or S-parameters, have beendeveloped for this purpose [1]. These S-parametersare defined for single-ended networks. S-parameterscan be used to describe differential networks, but astrict definition was not developed until Bockelmanand others addressed this issue [2]. Bockelman’swork also included a study on how to adapt single-ended S-parameters for use with differential circuits[2]. This adaptation, called “mixed-mode S-parameters,” addresses differential and common-mode operation, as well as the conversion betweenthe two modes of operation.This application note will explain the use of single-ended and mixed-mode S-parameters, and the basicconcepts of microwave measurement calibration.
上傳時(shí)間： 2014-03-25
上傳用戶：yyyyyyyyyy
Agilent AN 154 S-Parameter Design Application Note S參數(shù)的設(shè)計(jì)與應(yīng)用 The need for new high-frequency, solid-state circuitdesign techniques has been recognized both by microwaveengineers and circuit designers. These engineersare being asked to design solid state circuitsthat will operate at higher and higher frequencies.The development of microwave transistors andAgilent Technologies’ network analysis instrumentationsystems that permit complete network characterizationin the microwave frequency rangehave greatly assisted these engineers in their work.The Agilent Microwave Division’s lab staff hasdeveloped a high frequency circuit design seminarto assist their counterparts in R&D labs throughoutthe world. This seminar has been presentedin a number of locations in the United States andEurope.From the experience gained in presenting this originalseminar, we have developed a four-part videotape, S-Parameter Design Seminar. While the technologyof high frequency circuit design is everchanging, the concepts upon which this technologyhas been built are relatively invariant.The content of the S-Parameter Design Seminar isas follows:
標(biāo)簽： S參數(shù)
上傳時(shí)間： 2013-12-19
上傳用戶：aa54
解壓密碼：www.elecfans.com 隨著微電子技術(shù)的迅速發(fā)展以及集成電路規(guī)模不斷提高，對(duì)電路性能的設(shè)計(jì) 要求越來越嚴(yán)格，這勢(shì)必對(duì)用于大規(guī)模集成電路設(shè)計(jì)的EDA 工具提出越來越高的 要求。自1972 年美國加利福尼亞大學(xué)柏克萊分校電機(jī)工程和計(jì)算機(jī)科學(xué)系開發(fā) 的用于集成電路性能分析的電路模擬程序SPICE（Simulation Program with IC Emphasis）誕生以來，為適應(yīng)現(xiàn)代微電子工業(yè)的發(fā)展，各種用于集成電路設(shè)計(jì)的 電路模擬分析工具不斷涌現(xiàn)。HSPICE 是Meta-Software 公司為集成電路設(shè)計(jì)中 的穩(wěn)態(tài)分析，瞬態(tài)分析和頻域分析等電路性能的模擬分析而開發(fā)的一個(gè)商業(yè)化通 用電路模擬程序，它在柏克萊的SPICE（1972 年推出），MicroSim公司的PSPICE （1984 年推出）以及其它電路分析軟件的基礎(chǔ)上，又加入了一些新的功能，經(jīng) 過不斷的改進(jìn)，目前已被許多公司、大學(xué)和研究開發(fā)機(jī)構(gòu)廣泛應(yīng)用。HSPICE 可 與許多主要的EDA 設(shè)計(jì)工具，諸如Candence,Workview 等兼容，能提供許多重要 的針對(duì)集成電路性能的電路仿真和設(shè)計(jì)結(jié)果。采用HSPICE 軟件可以在直流到高 于100MHz 的微波頻率范圍內(nèi)對(duì)電路作精確的仿真、分析和優(yōu)化。在實(shí)際應(yīng)用中， HSPICE能提供關(guān)鍵性的電路模擬和設(shè)計(jì)方案，并且應(yīng)用HSPICE進(jìn)行電路模擬時(shí)， 其電路規(guī)模僅取決于用戶計(jì)算機(jī)的實(shí)際存儲(chǔ)器容量。 The HSPICE Integrator Program enables qualified EDA vendors to integrate their products with the de facto standard HSPICE simulator, HSPICE RF simulator, and WaveView Analyzer™. In addition, qualified HSPICE Integrator Program members have access to HSPICE integrator application programming interfaces (APIs). Collaboration between HSPICE Integrator Program members will enable customers to achieve more thorough design verification in a shorter period of time from the improvements offered by inter-company EDA design solutions.
標(biāo)簽： download hspice 2007
上傳時(shí)間： 2013-11-10
上傳用戶：123312
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-21
上傳用戶：wxqman
This application note describes how to implement the Bus LVDS (BLVDS) interface in the supported Altera ® device families for high-performance multipoint applications. This application note also shows the performance analysis of a multipoint application with the Cyclone III BLVDS example.
標(biāo)簽： Implementing LVDS 522 Bus
上傳時(shí)間： 2013-10-26
上傳用戶：蘇蘇蘇蘇
This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.
上傳時(shí)間： 2013-10-09
上傳用戶：guojin_0704
This application note provides users with a general understanding of the SVF and XSVF fileformats as they apply to Xilinx devices. Some familiarity with IEEE STD 1149.1 (JTAG) isassumed. For information on using Serial Vector Format (SVF) and Xilinx Serial Vector Format(XSVF) files in embedded programming applications
標(biāo)簽： Xilinx XAPP XSVF 503
上傳時(shí)間： 2015-01-02
上傳用戶：時(shí)代將軍
This application note contains a reference design consisting of HDL IP and Xilinx AdvancedConfiguration Environment (ACE) software utilities that give designers great flexibility increating in-system programming (ISP) solutions. In-system programming support allowsdesigners to revise existing designs, package the new bitstream programming files with theprovided software utilities, and update the remote system through the JTAG interface using theEmbedded JTAG ACE Player.
上傳時(shí)間： 2013-10-22
上傳用戶：gai928943
This application note describes how the existing dual-port block memories in the Spartan™-IIand Virtex™ families can be used as Quad-Port memories. This essentially involves a dataaccess time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the blockmemory in terms of bits per second will remain the same.
上傳時(shí)間： 2014-01-24
上傳用戶：15527161163
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