This lab exercise will introduce you to AccelDSP’s floating- to fixed-point conversion features. AccelDSP will automatically generate a fixed-point representation of a floating-point design. This process is controllable by using quantize directives.
MPLAB C30用戶指南(英文)
HIGHLIGHTSThe information covered in this chapter is as follows:• About this Guide• Recommended Reading• Troubleshooting• The Microchip Web Site• Development Systems Customer Notification Service• Customer Support
Document LayoutThe document layout is as follows:• Chapter 1: Compiler Overview – describes MPLAB C30, development tools andfeature set.• Chapter 2: Differences between MPLAB C30 and ANSI C – describes thedifferences between the C language supported by MPLAB C30 syntax and thestandard ANSI-89 C.• Chapter 3: Using MPLAB C30 – describes how to use the MPLAB C30 compilerfrom the command line.• Chapter 4: MPLAB C30 Runtime Environment – describes the MPLAB C30runtime model, including information on sections, initialization, memory models, thesoftware stack and much more.• Chapter 5: Data Types – describes MPLAB C30 integer, floating point and pointerdata types.• Chapter 6: Device Support Files – describes the MPLAB C30 header and registerdefinition files, as well as how to use with SFR’s.• Chapter 7: Interrupts – describes how to use interrupts.• Chapter 8: Mixing Assembly Language and C Modules – provides guidelines tousing MPLAB C30 with MPLAB ASM30 assembly language modules.
WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮點DSP算法實現(xiàn)方案：
High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮點DSP算法實現(xiàn)方案：
High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs
The Audio File Library provides a uniform programming interface to
standard digital audio file formats.
This library allows the processing of audio data to and from audio
files of many common formats (currently AIFF, AIFF-C, WAVE, NeXT/Sun
.snd/.au, IRCAM, AVR, Amiga IFF/8SVX, and NIST SPHERE). The library
also supports compression (currently G.711 mu-law and A-law and IMA and
MS ADPCM) as well as PCM formats of all flavors (signed and unsigned
integer, single- and double-precision floating point).
關于FPGA流水線設計的論文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.
Two functions, num2bin and bin2num are provided. num2bin takes a double and converts it to a binary string representation. bin2num is its inverse operation. It can be used in a numerical analysis course when floating point arithmetic is discussed.
This getting started exercise will guide you through the step-by-step process of transforming a MATLAB floating-point model into a hardware module that can be implemented in silicon (FPGA or ASIC). The design is a general purpose FIR filter taken from the AccelDSP Examples directory.
CCS編程環(huán)境 使用的是匯編加C的混合編程方法：
The programme of the Correlation Algorithm.
Using INT2 to get the input signal.
Array x, in first step, is the input signal produced by programme,
in next step, is the input signal get from A/D,
the length is 128, 32-bit floating point.
Array y, in first step, is the input signal produced by programme,
in next step, is the input signal get from A/D,
the length is 128, 32-bit floating point.
Array cor is the Correlation result, the length is 255, 32-bit floating point.
