#include <malloc.h> #include <stdio.h> #include <stdlib.h> #include <string.h> #define NULL 0 #define MaxSize 30 typedef struct athletestruct /*運(yùn)動(dòng)員*/ { char name[20]; int score; /*分?jǐn)?shù)*/ int range; /**/ int item; /*項(xiàng)目*/ }ATH; typedef struct schoolstruct /*學(xué)校*/ { int count; /*編號(hào)*/ int serial; /**/ int menscore; /*男選手分?jǐn)?shù)*/ int womenscore; /*女選手分?jǐn)?shù)*/ int totalscore; /*總分*/ ATH athlete[MaxSize]; /**/ struct schoolstruct *next; }SCH; int nsc,msp,wsp; int ntsp; int i,j; int overgame; int serial,range; int n; SCH *head,*pfirst,*psecond; int *phead=NULL,*pafirst=NULL,*pasecond=NULL; void create(); void input () { char answer; head = (SCH *)malloc(sizeof(SCH)); /**/ head->next = NULL; pfirst = head; answer = 'y'; while ( answer == 'y' ) { Is_Game_DoMain: printf("\nGET Top 5 when odd\nGET Top 3 when even"); printf("\n輸入運(yùn)動(dòng)項(xiàng)目序號(hào) (x<=%d):",ntsp); scanf("%d",pafirst); overgame = *pafirst; if ( pafirst != phead ) { for ( pasecond = phead ; pasecond < pafirst ; pasecond ++ ) { if ( overgame == *pasecond ) { printf("\n這個(gè)項(xiàng)目已經(jīng)存在請選擇其他的數(shù)字\n"); goto Is_Game_DoMain; } } } pafirst = pafirst + 1; if ( overgame > ntsp ) { printf("\n項(xiàng)目不存在"); printf("\n請重新輸入"); goto Is_Game_DoMain; } switch ( overgame%2 ) { case 0: n = 3;break; case 1: n = 5;break; } for ( i = 1 ; i <= n ; i++ ) { Is_Serial_DoMain: printf("\n輸入序號(hào) of the NO.%d (0<x<=%d): ",i,nsc); scanf("%d",&serial); if ( serial > nsc ) { printf("\n超過學(xué)校數(shù)目,請重新輸入"); goto Is_Serial_DoMain; } if ( head->next == NULL ) { create(); } psecond = head->next ; while ( psecond != NULL ) { if ( psecond->serial == serial ) { pfirst = psecond; pfirst->count = pfirst->count + 1; goto Store_Data; } else { psecond = psecond->next; } } create(); Store_Data: pfirst->athlete[pfirst->count].item = overgame; pfirst->athlete[pfirst->count].range = i; pfirst->serial = serial; printf("Input name:) : "); scanf("%s",pfirst->athlete[pfirst->count].name); } printf("\n繼續(xù)輸入運(yùn)動(dòng)項(xiàng)目(y&n)？"); answer = getchar(); printf("\n"); } } void calculate() /**/ { pfirst = head->next; while ( pfirst->next != NULL ) { for (i=1;i<=pfirst->count;i++) { if ( pfirst->athlete[i].item % 2 == 0 ) { switch (pfirst->athlete[i].range) { case 1:pfirst->athlete[i].score = 5;break; case 2:pfirst->athlete[i].score = 3;break; case 3:pfirst->athlete[i].score = 2;break; } } else { switch (pfirst->athlete[i].range) { case 1:pfirst->athlete[i].score = 7;break; case 2:pfirst->athlete[i].score = 5;break; case 3:pfirst->athlete[i].score = 3;break; case 4:pfirst->athlete[i].score = 2;break; case 5:pfirst->athlete[i].score = 1;break; } } if ( pfirst->athlete[i].item <=msp ) { pfirst->menscore = pfirst->menscore + pfirst->athlete[i].score; } else { pfirst->womenscore = pfirst->womenscore + pfirst->athlete[i].score; } } pfirst->totalscore = pfirst->menscore + pfirst->womenscore; pfirst = pfirst->next; } } void output() { pfirst = head->next; psecond = head->next; while ( pfirst->next != NULL ) { // clrscr(); printf("\n第%d號(hào)學(xué)校的結(jié)果成績:",pfirst->serial); printf("\n\n項(xiàng)目的數(shù)目\t學(xué)校的名字\t分?jǐn)?shù)"); for (i=1;i<=ntsp;i++) { for (j=1;j<=pfirst->count;j++) { if ( pfirst->athlete[j].item == i ) { printf("\n %d\t\t\t\t\t\t%s\n %d",i,pfirst->athlete[j].name,pfirst->athlete[j].score);break; } } } printf("\n\n\n\t\t\t\t\t\t按任意建 進(jìn)入下一頁"); getchar(); pfirst = pfirst->next; } // clrscr(); printf("\n運(yùn)動(dòng)會(huì)結(jié)果:\n\n學(xué)校編號(hào)\t男運(yùn)動(dòng)員成績\t女運(yùn)動(dòng)員成績\t總分"); pfirst = head->next; while ( pfirst->next != NULL ) { printf("\n %d\t\t %d\t\t %d\t\t %d",pfirst->serial,pfirst->menscore,pfirst->womenscore,pfirst->totalscore); pfirst = pfirst->next; } printf("\n\n\n\t\t\t\t\t\t\t按任意建結(jié)束"); getchar(); } void create() { pfirst = (struct schoolstruct *)malloc(sizeof(struct schoolstruct)); pfirst->next = head->next ; head->next = pfirst ; pfirst->count = 1; pfirst->menscore = 0; pfirst->womenscore = 0; pfirst->totalscore = 0; } void Save() {FILE *fp; if((fp = fopen("school.dat","wb"))==NULL) {printf("can't open school.dat\n"); fclose(fp); return; } fwrite(pfirst,sizeof(SCH),10,fp); fclose(fp); printf("文件已經(jīng)成功保存\n"); } void main() { system("cls"); printf("\n\t\t\t 運(yùn)動(dòng)會(huì)分?jǐn)?shù)統(tǒng)計(jì)\n"); printf("輸入學(xué)校數(shù)目 (x>= 5):"); scanf("%d",&nsc); printf("輸入男選手的項(xiàng)目(x<=20):"); scanf("%d",&msp); printf("輸入女選手項(xiàng)目(<=20):"); scanf("%d",&wsp); ntsp = msp + wsp; phead = (int *)calloc(ntsp,sizeof(int)); pafirst = phead; pasecond = phead; input(); calculate(); output(); Save(); }
標(biāo)簽： 源代碼
上傳時(shí)間： 2016-12-28
上傳用戶：150501
The writing of this book was prompted by two main developments in wireless communications in the past decade. First is the huge surge of research activities in physical-layer wireless communication theory. While this has been a subject of study since the 60’s, recent developments in the field, such as opportunistic and multi-input multi-output (MIMO) communication techniques, have brought completely new per- spectives on how to communicate over wireless channels.
標(biāo)簽： Communication Fundamentals Wireless of
上傳時(shí)間： 2020-05-27
上傳用戶：shancjb
An acronym for Multiple-In, Multiple-Out, MIMO communication sends the same data as several signals simultaneously through multiple antennas, while still utilizing a single radio channel. This is a form of antenna diversity, which uses multiple antennas to improve signal quality and strength of an RF link. The data is split into multiple data streams at the transmission point and recombined on the receive side by another MIMO radio configured with the same number of antennas. The receiver is designed to take into account the slight time difference between receptions of each signal, any additional noise or interference, and even lost signals.
標(biāo)簽： Understanding_the_Basics_of_MIMO
上傳時(shí)間： 2020-06-01
上傳用戶：shancjb
FPGA采樣AD9238數(shù)據(jù)并通過VGA波形顯示例程 Verilog邏輯源碼Quartus工程文件+文檔說明,FPGA型號(hào)Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。ADC 模塊型號(hào)為 AN9238，最大采樣率 65Mhz，精度為12 位。實(shí)驗(yàn)中把 AN9238 的 2 路輸入以波形方式在 HDMI 上顯示出來，我們可以用更加直觀的方式觀察波形，是一個(gè)數(shù)字示波器雛形。module top( input clk, input rst_n, output ad9238_clk_ch0, output ad9238_clk_ch1, input[11:0] ad9238_data_ch0, input[11:0] ad9238_data_ch1, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue);wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire grid_hs;wire grid_vs;wire grid_de;wire[7:0] grid_r;wire[7:0] grid_g;wire[7:0] grid_b;wire wave0_hs;wire wave0_vs;wire wave0_de;wire[7:0] wave0_r;wire[7:0] wave0_g;wire[7:0] wave0_b;wire wave1_hs;wire wave1_vs;wire wave1_de;wire[7:0] wave1_r;wire[7:0] wave1_g;wire[7:0] wave1_b;wire adc_clk;wire adc0_buf_wr;wire[10:0] adc0_buf_addr;wire[7:0] adc0_bu
上傳時(shí)間： 2021-10-27
上傳用戶：qingfengchizhu
FPGA讀寫SD卡讀取BMP圖片通過LCD顯示例程實(shí)驗(yàn) Verilog邏輯源碼Quartus工程文件+文檔說明,FPGA型號(hào)Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 實(shí)驗(yàn)簡介在前面的實(shí)驗(yàn)中我們練習(xí)了 SD 卡讀寫，VGA 視頻顯示等例程，本實(shí)驗(yàn)將 SD 卡里的 BMP 圖片讀出，寫入到外部存儲(chǔ)器，再通過 VGA、LCD 等顯示。本實(shí)驗(yàn)如果通過液晶屏顯示，需要有液晶屏模塊。2 實(shí)驗(yàn)原理在前面的實(shí)驗(yàn)中我們在 VGA、LCD 上顯示的是彩條，是 FPGA 內(nèi)部產(chǎn)生的數(shù)據(jù)，本實(shí)驗(yàn)將彩條替換為 SD 內(nèi)的 BMP 圖片數(shù)據(jù)，但是 SD 卡讀取速度遠(yuǎn)遠(yuǎn)不能滿足顯示速度的要求，只能先寫入外部高速 RAM，再讀出后給視頻時(shí)序模塊顯示module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24
標(biāo)簽： fpga
上傳時(shí)間： 2021-10-27
上傳用戶：
FPGA讀取OV5640攝像頭數(shù)據(jù)并通過VGA或LCD屏顯示輸出的Verilog邏輯源碼Quartus工程文件+文檔說明，F(xiàn)PGA型號(hào)Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上傳時(shí)間： 2021-12-18
上傳用戶：
基于FPGA設(shè)計(jì)的sdram讀寫測試實(shí)驗(yàn)Verilog邏輯源碼Quartus工程文件+文檔說明，DRAM選用海力士公司的 HY57V2562 型號(hào),容量為的 256Mbit,采用了 54 引腳的TSOP 封裝, 數(shù)據(jù)寬度都為 16 位, 工作電壓為 3.3V,并丏采用同步接口方式所有的信號(hào)都是時(shí)鐘信號(hào)。FPGA型號(hào)Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
標(biāo)簽： fpga sdram verilog quartus
上傳時(shí)間： 2021-12-18
上傳用戶：
ADS8329 Verilog fpga 驅(qū)動(dòng)源碼，2.7V 至 5.5V 16 位 1MSPS 串行模數(shù)轉(zhuǎn)換器 ADC芯片ADS8329數(shù)據(jù)采集的verilog代碼，已經(jīng)用在工程中，可以做為你的設(shè)計(jì)參考。( input clock, input timer_clk_r, input reset, output reg sample_over, output reg ad_convn, input ad_eocn, output reg ad_csn, output reg ad_clk, input ad_dout, output reg ad_din, output reg [15:0] ad_data_lock);reg [15:0] ad_data_old;reg [15:0] ad_data_new; reg [19:0] ad_data_temp; reg [15:0] ad_data;reg [4:0] ad_data_cnt;reg [4:0] ad_spi_cnt; reg [5:0] time_dly_cnt; parameter [3:0] state_mac_IDLE = 0, state_mac_0 = 1, state_mac_1 = 2, state_mac_2 = 3, state_mac_3 = 4, state_mac_4 = 5, state_mac_5 = 6, state_mac_6 = 7, state_mac_7 = 8, state_mac_8 = 9, state_mac_9 = 10, state_mac_10 = 11, state_mac_11 = 12, state_mac_12 = 13, state_mac_13 = 14, state_mac_14 = 15; reg [3:0] state_curr;reg [3:0] state_next;
標(biāo)簽： ads8329 verilog fpga 驅(qū)動(dòng)
上傳時(shí)間： 2022-01-30
上傳用戶：1208020161
Precision, Low Noise, CMOS, Rail-to-Rail, Input/Output Operational Amplifiers Data Sheet AD8605/AD8606/AD8608The AD8605, AD8606, and AD86081 are single, dual, and quad rail-to-rail input and output, single-supply amplifiers. They feature very low offset voltage, low input voltage and current noise, and wide signal bandwidth. They use the Analog Devices, Inc. patented DigiTrim? trimming technique, which achieves
標(biāo)簽： 運(yùn)算放大器
上傳時(shí)間： 2022-02-02
上傳用戶：
spi 通信的master部分使用的verilog語言實(shí)現(xiàn)，可以做為你的設(shè)計(jì)參考。module spi_master(rstb,clk,mlb,start,tdat,cdiv,din, ss,sck,dout,done,rdata); input rstb,clk,mlb,start; input [7:0] tdat; //transmit data input [1:0] cdiv; //clock divider input din; output reg ss; output reg sck; output reg dout; output reg done; output reg [7:0] rdata; //received dataparameter idle=2'b00; parameter send=2'b10; parameter finish=2'b11; reg [1:0] cur,nxt; reg [7:0] treg,rreg; reg [3:0] nbit; reg [4:0] mid,cnt; reg shift,clr;
標(biāo)簽： spi 通信 master verilog
上傳時(shí)間： 2022-02-03
上傳用戶：
蟲蟲下載站版權(quán)所有 京ICP備2021023401號(hào)-1
