iic總線控制器VHDL實(shí)現(xiàn)
-- VHDL Source Files:
i2c.vhd -- top level file
i2c_control.vhd -- control function for the I2C master/slave
shift.vhd -- shift register
uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC
upcnt4.vhd -- 4-bit up counter
i2c_timesim.vhd -- post-route I2C simulation netlist
* The keyboard is assumed to be a matrix having 4 rows by 6 columns. However, this code works for any
* matrix arrangements up to an 8 x 8 matrix. By using from one to three of the column inputs, the driver
* can support "SHIFT" keys. These keys are: SHIFT1, SHIFT2 and SHIFT3.
51單片機(jī)C語言多種點(diǎn)陣屏驅(qū)動(dòng)程序（開發(fā)軟件為keil C ---8字點(diǎn)陣屏左移程序，64_16點(diǎn)陣屏驅(qū)動(dòng)程序，上移顯示程序，左移顯示程序）51 monolithic integrated circuit C language many kinds of lattice screen driver (develops the software is keil C ---8 character lattice screen left shift procedure, the 64_16 lattice screen driver, uppers shift the display sequence, the left shift display sequence
PRINCIPLE: The UVE algorithm detects and eliminates from a PLS model (including from 1 to A components) those variables that do not carry any relevant information to model Y. The criterion used to trace the un-informative variables is the reliability of the regression coefficients: c_j=mean(b_j)/std(b_j), obtained by jackknifing. The cutoff level, below which c_j is considered to be too small, indicating that the variable j should be removed, is estimated using a matrix of random variables.The predictive power of PLS models built on the retained variables only is evaluated over all 1-a dimensions =(yielding RMSECVnew).
The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until it hits the pixel at the center. It then sticks and a new walker is started randomly at one of the 4 corners of the screen. The random number generators for x and y steps are XOR feedback shift registers (see also Hamblen, Appendix A). The VGA driver, PLL, and reset controller from the DE2 CDROM are necessary to compile this example. Note that you must push KEY0 to start the state machine.
DDR SDRAM控制器的VHDL源代碼，含詳細(xì)設(shè)計(jì)文檔。
The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect
choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock
Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS),
and Digital Frequency Synthesis (DFS) functions. This application note describes a controller
design for a 16-bit DDR SDRAM. The application note and reference design are enhanced
versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz,
16-bit data changes at both clock edges. The reference design is fully synthesizable and
achieves 133 MHz performance with automatic place and route tools.
neural network utility is a Neural Networks library for the
C++ Programmer. It is entirely object oriented and focuses
on reducing tedious and confusing problems of programming neural networks.
By this I mean that network layers are easily defined. An
entire multi-layer network can be created in a few lines, and
trained with two functions. Layers can be connected to one another
easily and painlessly.
GPS 接收程序 DEMO。
HsGpsDll Library 1.1
A GPS Control/Component for C/C++
HsGpsDll is a Windows Dynamic Link Library which provides access to any NMEA-183 compliant GPS receiver via a serial communications port. HsGpsDll is designed for use from Visual C, Visual Basic or other languages, capable of calling DLL functions. HsGpsDll allows a user application to read from a GPS device the current GPS position fix, velocity over ground (speed in kilometers per hour), plus number of of sattelites in view, current altitude (against mean sea level) and UTC date and time
