Nios 的用戶定義接口邏輯實(shí)例 有許多人問(wèn)我使用 Nios 的用戶定義接口邏輯怎么用，想了幾天決定設(shè)計(jì)一個(gè)實(shí)例來(lái)說(shuō)明。該例為一個(gè)使用 user to interface logic 設(shè)計(jì)的 PWM 實(shí)例，其中包括三個(gè)文件： plus32.v 是一個(gè)為 32bit nios 設(shè)計(jì)的 pwm 實(shí)例。 plus16.v 是一個(gè)為 16bit nios 設(shè)計(jì)的 pwm 實(shí)例。 test.s 是一個(gè)使用中斷調(diào)用 pwm 的匯編語(yǔ)言測(cè)試程序。以上模塊和程序均調(diào)試通過(guò)，并可穩(wěn)定工作。這里讓大家參考是使大家通過(guò)該例來(lái)真正理解 user to interface logic 設(shè)計(jì)方法，和nios 中通過(guò)匯編調(diào)用中斷的方法，所以超值喔。另外熱烈歡迎大家的指導(dǎo)。 注：在設(shè)計(jì) Nios 時(shí)，將你調(diào)用的 user to interface logic 插件重命名為 plus_0，這樣我的 test.s 可不作任何改動(dòng)，你就可用示波器通過(guò) nios 的 plus 管腳觀察到一個(gè)要求的輸出。
上傳時(shí)間： 2013-11-15
上傳用戶：cc1915
HCS12微控制器MC9S12DP256 第一步： 1) HCS12 技術(shù)概述2) Operating Modes工作模式3) Resource Mapping資源映射4) External Bus Interface外部總線接口5) Port Integration Module端口集成模塊6) Background Debug Mode背景調(diào)試模塊
上傳時(shí)間： 2013-12-20
上傳用戶：源碼3
The Controller Area Network (CAN) is a serial, asynchronous, multi-master communication protocol forconnecting electronic control modules, sensors and actuators in automotive and industrial applications.With the SJA1000, Philips Semiconductors provides a stand-alone CAN controller which is more than a simpleeplacement of the PCA82C200.Attractive features are implemented for a wide range of applications, supporting system optimization, diagnosisand maintenance.
標(biāo)簽： Stand-alone contro 1000 SJA
上傳時(shí)間： 2013-11-18
上傳用戶：yxgi5
The PCA9519 is a 4-channel level translating I2C-bus/SMBus repeater that enables theprocessor low voltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling the I2C-bus or SMBusmaximum capacitance of 400 pF on the higher voltage side. The SDA and SCL pins areover-voltage tolerant and are high-impedance when the PCA9519 is unpowered.
標(biāo)簽： 4channel transla level 9519
上傳時(shí)間： 2013-11-19
上傳用戶：jisiwole
The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for SMBus and I2C-bus applications. The PCA9557 consists of an 8-bit input port register, 8-bit output port register, and an I2C-bus/SMBus interface. It has low current consumption and a high-impedance open-drain output pin, IO0. The system master can enable the PCA9557’s I/O as either input or output by writing to the configuration register. The system master can also invert the PCA9557 inputs by writing to the active HIGH polarity inversion register. Finally, the system master can reset the PCA9557 in the event of a time-out by asserting a LOW in the reset input. The power-on reset puts the registers in their default state and initializes the I2C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without de-powering the part.
標(biāo)簽： C-bus SMBus reset port
上傳時(shí)間： 2014-01-18
上傳用戶：bs2005
The TJA1042 is a high-speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol controller and the physical two-wire CAN bus.The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing the differential transmit and receive capability to (amicrocontroller with) a CAN protocol controller.
標(biāo)簽： High-speed transce 1042 TJA
上傳時(shí)間： 2014-12-28
上傳用戶：氣溫達(dá)上千萬(wàn)的
The TJA1051 is a high-speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol controller and the physical two-wire CAN bus.The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing differential transmit and receive capability to (amicrocontroller with) a CAN protocol controller.
標(biāo)簽： High-speed transce 1051 TJA
上傳時(shí)間： 2013-10-17
上傳用戶：jisujeke
Although Stellaris microcontrollers have generous internal SRAM capabilities, certain applicationsmay have data storage requirements that exceed the 8 KB limit of the Stellaris LM3S8xx seriesdevices. Since microcontrollers do not have an external parallel data-bus, serial memory optionsmust be considered. Until recently, the ubiquitous serial EEPROM/flash device was the only serialmemory solution. The major limitations of EEPROM and flash technology are slow write speed, slowerase times, and limited write/erase endurance.Recently, serial SRAM devices have become available as a solution for high-speed dataapplications. The N256S08xxHDA series of devices, from AMI Semiconductor, offer 32 K x 8 bits oflow-power data storage, a fast Serial Peripheral Interface (SPI) serial bus, and unlimited write cycles.The parts are available in 8-pin SOIC and compact TSSOP packages.
標(biāo)簽： Adding Serial SRAM 32
上傳時(shí)間： 2013-10-14
上傳用戶：cxl274287265
The MAX3243E device consists of three line drivers, five line receivers, and a dual charge-pump circuit with±15-kV ESD (HBM and IEC61000-4-2, Air-Gap Discharge) and ±8-kV ESD (IEC61000-4-2, Contact Discharge)protection on serial-port connection pins. The device meets the requirements of TIA/EIA-232-F and provides theelectrical interface between an asynchronous communication controller and the serial-port connector. Thiscombination of drivers and receivers matches that needed for the typical serial port used in an IBM PC/AT, orcompatible. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-Vsupply. In addition, the device includes an always-active noninverting output (ROUT2B), which allowsapplications using the ring indicator to transmit data while the device is powered down. The device operates atdata signaling rates up to 250 kbit/s and a maximum of 30-V/ms driver output slew rate.
標(biāo)簽： MULTICHANNEL 5.5 TO RS
上傳時(shí)間： 2013-10-19
上傳用戶：ddddddd
The P82B96 offers many different ways in which it can be used as abus interface. In its simplest application it can be used as aninterface between bus systems operating from different supplyvoltages. Opto isolation between two bus systems is possible, andalso the availability of the Tx and Rx signals permits interfacing ofthe P82B96 with other bus systems which separate the forwardoutput path, from the backward input signal path.
標(biāo)簽： P82B96 Using inter the
上傳時(shí)間： 2013-10-11
上傳用戶：洛木卓
蟲蟲下載站版權(quán)所有 京ICP備2021023401號(hào)-1
