CAN與RS232轉(zhuǎn)換節(jié)點的設(shè)計與實現(xiàn) 介紹將CAN總線接口與RS232總線接口相互轉(zhuǎn)換的設(shè)計方法和2種總線電平轉(zhuǎn)換關(guān)系，實現(xiàn)CAN總線與各模塊的接口設(shè)計，制定了相應(yīng)的軟硬件設(shè)計方案，并給出軟件設(shè)計流程圖以及部分硬件設(shè)計原理圖。為CAN總線與RS232總線互聯(lián)提供了一種方法，對CAN總線與RS232總線接口設(shè)備的互聯(lián)和廣泛應(yīng)用的實現(xiàn)具有重要意義。關(guān)鍵詞：CAN總線；RS-232總線；串行通信Design and Realization of CAN and RS232 Transformation NodeZHOU Wei, CHENG Xiao-hong(Information Institute, Wuhan University of Technology, Wuhan 430070)【Abstract】This paper introduces one design method of the CAN bus interface and the RS232 bus interface interconversion, emphasizes two kindof bus level transformation relations, realizes the CAN bus and various modules connection design, formulates the design proposal of correspondingsoftware and hardware, and gives the flow chart of software design as well as the partial schematic diagram of hardware design. It providesonemethod for the CAN bus and the RS232 bus interconnection, has the vital significance to widespread application realization of the CAN busand theRS232 bus interface equipment interconnection.【Key words】CAN bus; RS-232 bus; serial communication
上傳時間： 2013-11-04
上傳用戶：leesuper
串行下載線的原理圖 SI Prog - Serial Interface for PonyProg
上傳時間： 2013-11-09
上傳用戶：zhishenglu
基于單片機的汽車多功能報警系統(tǒng)設(shè)計The Design of Automobile Multi-function AlarmingBased on Single Chip Computer劉法治趙明富寧睡達(河 南 科 技 學 院 ，新 鄉(xiāng) 453 00 3)摘要介紹了一種基于單片機控制的汽車多功能報警系統(tǒng)，它能對汽車的潤滑系統(tǒng)油壓、制動系統(tǒng)氣壓、冷卻系統(tǒng)溫度、輪胎欠壓及防盜進行自動檢測，并在發(fā)現(xiàn)異常情況時，發(fā)出聲光報警。闡述了該報警系統(tǒng)的硬件組成及軟件設(shè)計方法。關(guān)鍵詞單片機傳感器數(shù)模轉(zhuǎn)換報警Abstract Am ulti-fimctiona utomobilea larnungs ystemb asedo ns inglec hipc omputerco ntorlis in torducedin th isp aper.Th eo ilpr essuero flu bricatesystem, air pressure of braking system, temperature of cooling system, under pressure of tyre and guard against theft， detected automaticaly場thesystem. Audio and visual alarms wil be provided under abnormal conditions廠The hardware composition and software design of the system， described.Keywords Singlec hipc omputer Sensor Digital-t-oanaloguec onversion Alarmin 汽車多功能報苦器硬件系統(tǒng)設(shè)計根據(jù) 系 統(tǒng) 實際需要和產(chǎn)品性價比，選用ATMEL公司新生產(chǎn)的采用CMOs工藝的低功耗、高性能8位單片機AT89S52作為系統(tǒng)的控制器。AT89S52的片內(nèi)有8k Bytes LSP Flash閃爍存儲器，可進行100(〕次寫、擦除操作;256Bytes內(nèi)部數(shù)據(jù)存儲器(RAM);3 2 根可編程輸N輸出線;2個可編程全雙工串行通道;看門狗(WTD)電路等。系統(tǒng)由傳感器、單片機、模數(shù)轉(zhuǎn)換器、無線信號發(fā)射電路、指示燈驅(qū)動電路、聲光報警驅(qū)動電KD一9563，發(fā)出三聲二閃光。并觸發(fā)一個高電平，驅(qū)動無線信號發(fā)射電路。
上傳時間： 2013-11-09
上傳用戶：gxmm
基于USB接口的數(shù)據(jù)采集模塊的設(shè)計與實現(xiàn)Design and Implementation of USB-Based Data Acquisition Module路 永 伸(天津科技大學電子信息與自動化學院，天津300222)摘要文中給出基于USB接口的數(shù)據(jù)采集模塊的設(shè)計與實現(xiàn)。硬件設(shè)計采用以Adpc831與PDIUSBDI2為主的器件進行硬件設(shè)計，采用Windriver開發(fā)USB驅(qū)動，并用Visual C十十6.0對主機軟件中硬件接口操作部分進行動態(tài)鏈接庫封裝。關(guān)鍵詞USB 數(shù)據(jù)采集Adpc831 PDNSBDI2 Windriver動態(tài)鏈接庫Abstract T hed esigna ndim plementaitono fU SB-BasedD ataA cquisiitonM oduleis g iven.Th ec hips oluitonm ainlyw ithA dpc831a ndP DTUSBD12i sused for hardware design. The USB drive is developed場Wmdriver, and the operation on the hardware interface is packaged into Dynamic Link Libraries場Visual C++6.0. Keywords USB DataA cquisition Adttc831 PDfUSBD12 Windriver0 引言US B總 線 是新一代接口總線，最初推出的目的是為了統(tǒng)一取代PC機的各類外設(shè)接口，迄今經(jīng)歷了1.0,1.1與2.0版本3個標準。在國內(nèi)基于USB總線的相關(guān)設(shè)計與開發(fā)也得到了快速的發(fā)展，很多設(shè)計者從各自的應(yīng)用領(lǐng)域，用不同方案設(shè)計出了相應(yīng)的裝置[1,2]。數(shù)據(jù)采集是工業(yè)控制中一個普遍而重要的環(huán)節(jié)，因此開發(fā)基于USB接口的數(shù)據(jù)采集模塊具有很強的現(xiàn)實應(yīng)用意義。雖然 US B總線標準已經(jīng)發(fā)展到2.0版本，但由于工業(yè)控制現(xiàn)場干擾信號的情況比較復(fù)雜，高速數(shù)據(jù)傳輸?shù)目煽啃圆蝗菀妆槐ＷC，并且很多場合對數(shù)據(jù)采集的實時性要求并不高，開發(fā)2.0標準產(chǎn)品的成本又較1.1標準產(chǎn)品高，所以筆者認為，在工業(yè)控制領(lǐng)域，目前開發(fā)基于USB總線1.1標準實現(xiàn)的數(shù)據(jù)采集模塊的實用意義大于相應(yīng)2.0標準模塊。
標簽： USB 接口 數(shù)據(jù)采集模塊
上傳時間： 2013-10-23
上傳用戶：q3290766
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構(gòu)
上傳時間： 2013-11-13
上傳用戶：瓦力瓦力hong
Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.
標簽： PicoBlaze Create Master Xilinx
上傳時間： 2013-11-05
上傳用戶：a6697238
This application note describes how to implement the Bus LVDS (BLVDS) interface in the supported Altera ® device families for high-performance multipoint applications. This application note also shows the performance analysis of a multipoint application with the Cyclone III BLVDS example.
標簽： Implementing LVDS 522 Bus
上傳時間： 2013-11-10
上傳用戶：frank1234
This application note explains the XC9500™/XL/XV Boundary Scan interface anddemonstrates the software available for programming and testing XC9500/XL/XV CPLDs. Anappendix summarizes the iMPACT software operations and provides an overview of theadditional operations supported by XC9500/XL/XV CPLDs for in-system programming.
上傳時間： 2013-11-15
上傳用戶：fengweihao158@163.com
This application note contains a reference design consisting of HDL IP and Xilinx AdvancedConfiguration Environment (ACE) software utilities that give designers great flexibility increating in-system programming (ISP) solutions. In-system programming support allowsdesigners to revise existing designs, package the new bitstream programming files with theprovided software utilities, and update the remote system through the JTAG interface using theEmbedded JTAG ACE Player.
上傳時間： 2013-11-14
上傳用戶：JIMMYCB001
The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus).
上傳時間： 2013-10-27
上傳用戶：zoudejile
蟲蟲下載站版權(quán)所有 京ICP備2021023401號-1
