The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct with minimal performance penalty. With their 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available fast GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications. Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.
標(biāo)簽： lpc datasheet 2292 2294
上傳時(shí)間： 2014-12-30
上傳用戶：aysyzxzm
針對(duì)解決OpenCV人臉檢測(cè)模塊在Android平臺(tái)編譯和移植的問(wèn)題，提出一種利用JNI技術(shù)（Java Native Interface）調(diào)用OpenCV以及采用Android NDK（Native Development Kit）生成共享庫(kù)的目標(biāo)檢測(cè)方法。文中從分析利用Android NDK編譯Android平臺(tái)所需要的OpenCV靜態(tài)庫(kù)的問(wèn)題入手，詳細(xì)闡述了利用JNI調(diào)用OpenCV相關(guān)函數(shù)的具體步驟。經(jīng)過(guò)多次試驗(yàn)，證明該人臉檢測(cè)模塊的平均檢測(cè)時(shí)間為1 280 ms，具有較高的檢測(cè)速度和檢測(cè)精度。
標(biāo)簽： Android OpenCV 人臉檢測(cè)
上傳時(shí)間： 2013-12-10
上傳用戶：15736969615
Abstract: This article describes the Antenna Interface Standards Group (AISG) standard in telecommunications and details itshardware implementation. It explains how a fully integrated transceiver such as the MAX9947 can help reduce space and cost, andsolve bus arbitrations in base-station tower equipment.
標(biāo)簽： AISG 硬件 分立收發(fā)器 控制系統(tǒng)
上傳時(shí)間： 2014-12-30
上傳用戶：wangchong
在研究傳統(tǒng)家用燃?xì)鈭?bào)警器的基礎(chǔ)上，以ZigBee協(xié)議為平臺(tái)，構(gòu)建mesh網(wǎng)狀網(wǎng)絡(luò)實(shí)現(xiàn)網(wǎng)絡(luò)化的智能語(yǔ)音報(bào)警系統(tǒng)。由于傳感器本身的溫度和實(shí)際環(huán)境溫度的影響，傳感器標(biāo)定后采用軟件補(bǔ)償方法。為了減少系統(tǒng)費(fèi)用，前端節(jié)點(diǎn)采用半功能節(jié)點(diǎn)設(shè)備，路由器和協(xié)調(diào)器采用全功能節(jié)點(diǎn)設(shè)備，構(gòu)建mesh網(wǎng)絡(luò)所形成的家庭內(nèi)部報(bào)警系統(tǒng)，通過(guò)通用的電話接口連接到外部的公用電話網(wǎng)絡(luò)，啟動(dòng)語(yǔ)音模塊進(jìn)行報(bào)警。實(shí)驗(yàn)結(jié)果表明，在2.4 GHz頻率下傳輸，有墻等障礙物的情況下，節(jié)點(diǎn)的傳輸距離大約為35 m，能夠滿足家庭需要，且系統(tǒng)工作穩(wěn)定，但在功耗方面仍需進(jìn)一步改善。 Abstract: On the basis of studying traditional household gas alarm system, this paper proposed the platform for the ZigBee protocol，and constructed mesh network to achieve network-based intelligent voice alarm system. Because of the sensor temperature and the actual environment temperature, this system design used software compensation after calibrating sensor. In order to reduce system cost, semi-functional node devices were used as front-end node, however, full-function devices were used as routers and coordinator，constructed alarm system within the family by building mesh network，connected to the external public telephone network through the common telephone interface, started the voice alarm module. The results indicate that nodes transmit about 35m in the distance in case of walls and other obstacles by 2.4GHz frequency transmission, this is able to meet family needs and work steadily, but still needs further improvement in power consumption.
標(biāo)簽： ZigBee 無(wú)線智能 家 報(bào)警系統(tǒng)
上傳時(shí)間： 2013-10-30
上傳用戶：swaylong
通過(guò)比較各種隔離數(shù)字通信的特點(diǎn)和應(yīng)用范圍，指出塑料光纖在隔離數(shù)字通信中的優(yōu)勢(shì)。使用已經(jīng)標(biāo)準(zhǔn)化的TOSLINK接口，有利于節(jié)省硬件開(kāi)發(fā)成本和簡(jiǎn)化設(shè)計(jì)難度。給出了塑料光纖的硬件驅(qū)動(dòng)電路，說(shuō)明設(shè)計(jì)過(guò)程中的注意事項(xiàng)，對(duì)光收發(fā)模塊的電壓特性和頻率特性進(jìn)行全面試驗(yàn)，并給出SPI口使用塑料光纖隔離通信的典型應(yīng)用電路圖。試驗(yàn)結(jié)果表明，該設(shè)計(jì)可為電力現(xiàn)場(chǎng)、電力電子及儀器儀表的設(shè)計(jì)提供參考。 Abstract: y comparing characteristics and applications area of various isolated digital communications， this article indicates advantages of plastic optical fiber in isolated digital communications. Using the standardized TOSLINK interface， it helps to control costs and difficulty in hardware development and design. Then it gives the hardware driver circuit of plastic optical fiber module， explains the noticed details in design process， gives results on the basis of the optical transceiver module voltage characteristics and frequency characteristics tests. Finally，it gives typical application circuit of the SPI communication port by using plastic optical fiber isolation .The results show that this design can be referenced for the power field， power electronics and instrumentation design.
標(biāo)簽： 塑料光纖 高壓隔離 通信 接口設(shè)計(jì)
上傳時(shí)間： 2014-01-10
上傳用戶：gundan
同步技術(shù)是跳頻通信系統(tǒng)的關(guān)鍵技術(shù)之一，尤其是在快速跳頻通信系統(tǒng)中，常規(guī)跳頻通信通過(guò)同步字頭攜帶相關(guān)碼的方法來(lái)實(shí)現(xiàn)同步，但對(duì)于快跳頻來(lái)說(shuō)，由于是一跳或者多跳傳輸一個(gè)調(diào)制符號(hào)，難以攜帶相關(guān)碼。對(duì)此引入雙跳頻圖案方法，提出了一種適用于快速跳頻通信系統(tǒng)的同步方案。采用短碼攜帶同步信息，克服了快速跳頻難以攜帶相關(guān)碼的困難。分析了同步性能，仿真結(jié)果表明該方案同步時(shí)間短、虛警概率低、捕獲概率高，同步性能可靠。 Abstract: Synchronization is one of the key techniques to frequency-hopping communication system， especially in the fast frequency hopping communication system. In conventional frequency hopping communication systems， synchronization can be achieved by synchronization-head which can be used to carry the synchronization information， but for the fast frequency hopping， Because modulation symbol is transmitted by per hop or multi-hop， it is difficult to carry the correlation code. For the limitation of fast frequency hopping in carrying correlation code， a fast frequency-hopping synchronization scheme with two hopping patterns is proposed. The synchronization information is carried by short code， which overcomes the difficulty of correlation code transmission in fast frequency-hopping. The performance of the scheme is analyzed， and simulation results show that the scheme has the advantages of shorter synchronization time， lower probability of false alarm， higher probability of capture and more reliable of synchronization.
標(biāo)簽： 快速跳頻 同步技術(shù) 通信系統(tǒng)
上傳時(shí)間： 2013-11-23
上傳用戶：mpquest
The NXP LPC314x combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, three channel10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted atconsumer, industrial, medical, and communication markets. To optimize system powerconsumption, the LPC314x have multiple power domains and a very flexible ClockGeneration Unit (CGU) that provides dynamic clock gating and scaling.
上傳時(shí)間： 2013-10-11
上傳用戶：yuchunhai1990
The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals. The ARMCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM data memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external memory controller, and multiple digital andanalog peripherals.
標(biāo)簽： Cortex-M 1850 LPC 內(nèi)核微控制器
上傳時(shí)間： 2014-12-31
上傳用戶：zhuoying119
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
上傳時(shí)間： 2013-10-28
上傳用戶：15501536189
Today in many applications such as network switches, routers, multi-computers,and processor-memory interfaces, the ability to integrate hundreds of multi-gigabit I/Os is desired to make better use of the rapidly advancing IC technology.
標(biāo)簽： 時(shí)鐘恢復(fù) 英文
上傳時(shí)間： 2013-10-30
上傳用戶：ysjing
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