DDR SDRAM控制器的VHDL源代碼，含詳細設計文檔。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application Note describes a controller design for a 16-bit DDR SDRAM. The application Note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上傳時間： 2014-11-01
上傳用戶：l254587896
*** *** *** *** *** *** ***** ** Two wire/I2C Bus READ/WRITE Sample Routines of Microchip s ** 24Cxx / 85Cxx serial CMOS EEPROM interfacing to a ** PIC16C54 8-bit CMOS single chip microcomputer ** Revsied Version 2.0 (4/2/92). ** ** Part use = PIC16C54-XT/JW ** Note: 1) All timings are based on a reference crystal frequency of 2MHz ** which is equivalent to an instruction cycle time of 2 usec. ** 2) Address and literal values are read in octal unless otherwise ** specified.
標簽： Microchip Routines Sample WRITE
上傳時間： 2013-12-27
上傳用戶：ljmwh2000
This book explains how to write device drivers for the newest members of the MicrosoftWindows family of operating systems using the Windows Driver Model (WDM). In this Introduction, I ll explain who should be reading this book, the organization of the book, and how to use the book most effectively. You ll also find a Note on errors and a section on other resources you can use to learn about driver programming. Looking ahead, Chapter 1 explains how the two main branches of the Windows family operate internally, what a WDM device driver is, and how it relates to the rest of Windows.
標簽： MicrosoftWindows the explains drivers
上傳時間： 2014-01-04
上傳用戶：dongqiangqiang
The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontroller. It is not, and is not intended as, a high fidelity circuit simulation. This package includes the following files. Note that the license agreement is stated in the main VHDL file, PICCPU.VHD and common questions are answered in the file SYNTHPIC.TXT Files: README.TXT This file.. SYNTHPIC.TXT Questions and Answers PICCPU.VHD Main processor VHDL file PICALU.VHD ALU for the PICCPU PICREGS.VHD Data memory PICROM.VHD Program memory (created by HEX2VHDL utility) PICTEST.VHD Simple test bench I used to do testing (optional) PICTEST.CMD My Viewlogic ViewSim command file (again, optional) TEST1.ASM First program I assembled and ran on it. TEST2.ASM Another test program.. TEST3.ASM Yet another.. TEST4.ASM Yet another.. TEST5.ASM Yet another.. TEST6.ASM Yet another.. HEX2VHDL.CPP Utility for converting
標簽： synthesizable microcontro Synthetic PIC
上傳時間： 2013-12-22
上傳用戶：妄想演繹師
In this article, I will explain how to create UDP packets and then send them to a remote server through the Internet using WinPCap for Windows. The code has been tested to work with Windows XP SP2 and Vista SP1 on Linksys routers, and on Toshiba modems connected directly to the Internet. Please Note that the code here is very minimalistic, and can be greatly expanded depending on your needs. The reason I use WinPCap in this article is that it solves the issue of Winsock for Windows (XP SP2 and above) not allowing raw UDP packets to be sent (in Linux, you can just use regular sockets). With WinPcap, it is possible to specify your own source IP and source hardware addresses in packets.
標簽： article explain packets create
上傳時間： 2013-12-12
上傳用戶：x4587
c pgm to find redundant paths in a graph.Many fault-tolerant network algorithms rely on an underlying assumption that there are possibly distinct network paths between a source-destination pair. Given a directed graph as input, write a program that uses depth-first search to determine all such paths. Note that, these paths are not vertex-disjoint i.e., the vertices may repeat but they are all edge-disjoint i.e., no two paths have the same edges. The input is the adjacency matrix of a directed acyclic graph and a pair(s) of source and destination vertices and the output should be the number of such disjoint paths and the paths themselves on separate lines. In case of multiple paths the output should be in order of paths with minimum vertices first. In case of tie the vertex number should be taken in consideration for ordering.
標簽： fault-tolerant algorithms redundant underlyin
上傳時間： 2013-12-18
上傳用戶：jkhjkh1982
R1EX24xxx series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). They realize high speed, low power consumption and a high level of reliability by employing advanced MNOS memory technology and CMOS process and low voltage circuitry technology. They also have a 128-byte page programming function to make their write operation faster. Note: Renesas Technology鈥檚 serial EEPROM are authorized for using consumer applications such as cellular phone, camcorders, audio equipment. Therefore, please contact Renesas Technology鈥檚 sales office before using industrial applications such as automotive systems, embedded controllers, and meters
標簽： Electrically Programmable interface Erasable
上傳時間： 2014-01-07
上傳用戶：xiaohuanhuan
I ll probably write up a short article next week outlining how the ActionScript works, so people can modify it, and work with it more easily in Flex. You can download the component and source code here. There are some instructions in the FLA on how to use it. Note that this is not a compiled component, so it won t show up in the components panel. You will have to copy the component, and the source file into your project. If anyone really wants a compiled version, let me know and I can provide one. As always, I d love to hear how people use it, and would appreciate it if you would post back to the comments if you make any significant modifications so that other people can benefit from them.
標簽： ActionScript outlining probably article
上傳時間： 2017-04-20
上傳用戶：c12228
The use of hardware description languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level description not only increases design productivity, but also provides unique advantages for design verification. The most dominant HDLs today are Verilog and VHDL. This application Note illustrates the use of Verilog in the design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).
標簽： increasingly description designing languages
上傳時間： 2014-01-08
上傳用戶：小草123
This file is distributed in the hope that it will be useful, but WITHOUT * WARRANTY OF ANY KIND. * * Author(s): Ole Saether * * DESCRIPTION: * * Hello World program. Please Note that this program runs the internal 8051 * on the default power up frequency of 4MHz. See ex3c.c for an example on how * to switch to 16MHz. * * The functionality is the same as in ex1a.asm. * * COMPILER: * * This program has been tested with Keil V7.07a. * * $Revision: 3 $ *
標簽： distributed WARRANTY WITHOUT useful
上傳時間： 2017-05-17
上傳用戶：515414293
