This effort started as an answer to the numerous questions the authors have repeatedly had to answer about electrostatic discharge (ESD) protection and input/OUTPUT (1/0) designs. In the past no comprehensive book existed suffi- ciently covering these areas, and these topics were rarely taught in engineering schools. Thus first-time I/O and ESD protection designers have had consider- able trouble getting started. This book is in part an answer to such needs.
上傳時間： 2020-06-05
上傳用戶：shancjb
Recent work has shown that convolutional networks can be substantially deeper, more accurate, and efficient to train if they contain shorter connections between layers close to the input and those close to the OUTPUT. In this paper, we embrace this observation and introduce the Dense Convo- lutional Network (DenseNet), which connects each layer to every other layer in a feed-forward fashion.
標簽： Convolutional Connected Networks Densely
上傳時間： 2020-06-10
上傳用戶：shancjb
lm75A溫度數(shù)字轉(zhuǎn)換器 FPGA讀寫實驗Verilog邏輯源碼Quartus工程文件+文檔資料,FPGA為CYCLONE4系列中的EP4CE6E22C8. 完整的工程文件，可以做為你的學(xué)習(xí)設(shè)計參考。LM75A 是一個使用了內(nèi)置帶隙溫度傳感器和模數(shù)轉(zhuǎn)換技術(shù)的溫度數(shù)字轉(zhuǎn)換器。它也是一個溫度檢測器，可提供一個過熱檢測輸出。LM75A 包含許多數(shù)據(jù)寄存器：配置寄存器用來存儲器件的某些配置，如器件的工作模式、OS 工作模式、OS 極性和OS 故障隊列等（在功能描述一節(jié)中有詳細描述）；溫度寄存器（Temp），用來存儲讀取的數(shù)字溫度；設(shè)定點寄存器（Tos & Thyst），用來存儲可編程的過熱關(guān)斷和滯后限制，器件通過2 線的串行I2C 總線接口與控制器通信。LM75A 還包含一個開漏輸出（OS），當溫度超過編程限制的值時該輸出有效。LM75A 有3 個可選的邏輯地址管腳，使得同一總線上可同時連接8個器件而不發(fā)生地址沖突。LM75A 可配置成不同的工作條件。它可設(shè)置成在正常工作模式下周期性地對環(huán)境溫度進行監(jiān)控或進入關(guān)斷模式來將器件功耗降至最低。OS 輸出有2 種可選的工作模式：OS 比較器模式和OS 中斷模式。OS 輸出可選擇高電平或低電平有效。故障隊列和設(shè)定點限制可編程，為了激活OS 輸出，故障隊列定義了許多連續(xù)的故障。溫度寄存器通常存放著一個11 位的二進制數(shù)的補碼，用來實現(xiàn)0.125℃的精度。這個高精度在需要精確地測量溫度偏移或超出限制范圍的應(yīng)用中非常有用。正常工作模式下，當器件上電時，OS 工作在比較器模式，溫度閾值為80℃，滯后75℃，這時，LM75A就可用作一個具有以上預(yù)定義溫度設(shè)定點的獨立的溫度控制器。module LM75_SEG_LED ( //input input sys_clk ,input sys_rst_n ,inout sda_port ,//OUTPUT OUTPUT wire seg_c1 ,OUTPUT wire seg_c2 ,OUTPUT wire seg_c3 ,OUTPUT wire seg_c4 ,OUTPUT reg seg_a ,OUTPUT reg seg_b ,OUTPUT reg seg_c ,OUTPUT reg seg_e ,OUTPUT reg seg_d ,OUTPUT reg seg_f ,OUTPUT reg seg_g ,OUTPUT reg seg_h , OUTPUT reg clk_sclk );//parameter define parameter WIDTH = 8;parameter SIZE = 8;//reg define reg [WIDTH-1:0] counter ;reg [9:0] counter_div ;reg clk_50k ;reg clk_200k ;reg sda ;reg enable ;
標簽： lm75a 數(shù)字轉(zhuǎn)換器 fpga verilog
上傳時間： 2021-10-27
上傳用戶：
FPGA采樣AD9238數(shù)據(jù)并通過VGA波形顯示例程 Verilog邏輯源碼Quartus工程文件+文檔說明,FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。ADC 模塊型號為 AN9238，最大采樣率 65Mhz，精度為12 位。實驗中把 AN9238 的 2 路輸入以波形方式在 HDMI 上顯示出來，我們可以用更加直觀的方式觀察波形，是一個數(shù)字示波器雛形。module top( input clk, input rst_n, OUTPUT ad9238_clk_ch0, OUTPUT ad9238_clk_ch1, input[11:0] ad9238_data_ch0, input[11:0] ad9238_data_ch1, //vga OUTPUT OUTPUT vga_out_hs, //vga horizontal synchronization OUTPUT vga_out_vs, //vga vertical synchronization OUTPUT[4:0] vga_out_r, //vga red OUTPUT[5:0] vga_out_g, //vga green OUTPUT[4:0] vga_out_b //vga blue);wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire grid_hs;wire grid_vs;wire grid_de;wire[7:0] grid_r;wire[7:0] grid_g;wire[7:0] grid_b;wire wave0_hs;wire wave0_vs;wire wave0_de;wire[7:0] wave0_r;wire[7:0] wave0_g;wire[7:0] wave0_b;wire wave1_hs;wire wave1_vs;wire wave1_de;wire[7:0] wave1_r;wire[7:0] wave1_g;wire[7:0] wave1_b;wire adc_clk;wire adc0_buf_wr;wire[10:0] adc0_buf_addr;wire[7:0] adc0_bu
上傳時間： 2021-10-27
上傳用戶：qingfengchizhu
FPGA讀寫SD卡讀取BMP圖片通過LCD顯示例程實驗 Verilog邏輯源碼Quartus工程文件+文檔說明,FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 實驗簡介在前面的實驗中我們練習(xí)了 SD 卡讀寫，VGA 視頻顯示等例程，本實驗將 SD 卡里的 BMP 圖片讀出，寫入到外部存儲器，再通過 VGA、LCD 等顯示。本實驗如果通過液晶屏顯示，需要有液晶屏模塊。2 實驗原理在前面的實驗中我們在 VGA、LCD 上顯示的是彩條，是 FPGA 內(nèi)部產(chǎn)生的數(shù)據(jù)，本實驗將彩條替換為 SD 內(nèi)的 BMP 圖片數(shù)據(jù)，但是 SD 卡讀取速度遠遠不能滿足顯示速度的要求，只能先寫入外部高速 RAM，再讀出后給視頻時序模塊顯示module top( input clk, input rst_n, input key1, OUTPUT [5:0] seg_sel, OUTPUT [7:0] seg_data, OUTPUT vga_out_hs, //vga horizontal synchronization OUTPUT vga_out_vs, //vga vertical synchronization OUTPUT[4:0] vga_out_r, //vga red OUTPUT[5:0] vga_out_g, //vga green OUTPUT[4:0] vga_out_b, //vga blue OUTPUT sd_ncs, //SD card chip select (SPI mode) OUTPUT sd_dclk, //SD card clock OUTPUT sd_mosi, //SD card controller data OUTPUT input sd_miso, //SD card controller data input OUTPUT sdram_clk, //sdram clock OUTPUT sdram_cke, //sdram clock enable OUTPUT sdram_cs_n, //sdram chip select OUTPUT sdram_we_n, //sdram write enable OUTPUT sdram_cas_n, //sdram column address strobe OUTPUT sdram_ras_n, //sdram row address strobe OUTPUT[1:0] sdram_dqm, //sdram data enable OUTPUT[1:0] sdram_ba, //sdram bank address OUTPUT[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24
標簽： fpga
上傳時間： 2021-10-27
上傳用戶：
Research on microwave power amplififiers has gained a growing importance demanded by the many continuously developing applications which require such subsystem performance. A broad set of commercial and strategic systems in fact have their overall performance boosted by the power amplififier, the latter becoming an enabling component wherever its effificiency and OUTPUT power actually allows functionalities and operating modes previously not possible. This is the case for the many wireless systems and battery-operated systems that form the substrate of everyday life, but also of high-performance satellite and dual-use systems.
上傳時間： 2021-10-30
上傳用戶：得之我幸78
基于TMS320F2812 光伏并網(wǎng)發(fā)電模擬裝置PROTEL設(shè)計原理圖+PCB+軟件源碼+WORD論文文檔,硬件采用2層板設(shè)計，PROTEL99SE 設(shè)計的工程文件，包括完整的原理圖和PCB文件，可以做為你的學(xué)習(xí)設(shè)計參考。 摘要：本文實現(xiàn)了一個基于TMS320F2812 DSP芯片的光伏并網(wǎng)發(fā)電模擬裝置，采用直流穩(wěn)壓源和滑動變阻器來模擬光伏電池。通過TMS320F2812 DSP芯片ADC模塊實時采樣模擬電網(wǎng)電壓的正弦參考信號、光伏電池輸出電壓、負載電壓電流反饋信號等。經(jīng)過數(shù)據(jù)處理后，用PWM模塊產(chǎn)生實時的SPWM 波，控制MOSFET逆變?nèi)珮蜉敵稣也ā１疚挠肞I控制算法實現(xiàn)了輸出信號對給定模擬電網(wǎng)電壓的正弦參考信號的頻率和相位跟蹤，用恒定電壓法實現(xiàn)了光伏電池最大功率點跟蹤（MPPT），從而達到模擬并網(wǎng)的效果。另外本裝置還實現(xiàn)了光伏電池輸出欠壓、負載過流保護功能以及光伏電池輸出欠壓、過流保護自恢復(fù)功能、聲光報警功能、孤島效應(yīng)的檢測、保護與自恢復(fù)功能。系統(tǒng)測試結(jié)果表明本設(shè)計完全滿定設(shè)計要求。關(guān)鍵詞：光伏并網(wǎng)，MPPT，DSP Photovoltaic Grid-connected generation simulator Zhangyuxin，Tantiancheng，Xiewuyang(College of Electrical Engineering, Chongqing University)Abstract: This paper presents a photovoltaic grid-connected generation simulator which is based on TMS320F2812 DSP, with a DC voltage source and a variable resistor to simulate the characteristic of photovoltaic cells. We use the internal AD converter to real-time sampling the referenced grid voltage signal, OUTPUTting voltage of photovoltaic, feedback OUTPUTting voltage and current signal. The PWM module generates SVPWM according to the calculation of the real-time sampling data, to control the full MOSFET inverter bridge OUTPUT sine wave. We realized that the OUTPUT voltage of the simulator can track the frequency and phase of the referenced grid voltage with PI regulation, and the maximum photovoltaic power tracking with constant voltage regulation, thereby achieved the purpose of grid-connected simulation. Additionally, this device has the over-voltage and over-current protection, audible and visual alarm, islanding detecting and protection, and it can recover automatically. The testing shows that our design is feasible.Keywords: Photovoltaic Grid-connected，MPPT，DSP 目錄引言 11. 方案論證 11.1. 總體介紹 11.2. 光伏電池模擬裝置 11.3. DC-AC逆變橋 11.4. MOSFET驅(qū)動電路方案 21.5. 逆變電路的變頻控制方案 22. 理論分析與計算 22.1. SPWM產(chǎn)生 22.1.1. 規(guī)則采樣法 22.1.2. SPWM 脈沖的計算公式 32.1.3. SPWM 脈沖計算公式中的參數(shù)計算 32.1.4. TMS320F2812 DSP控制器的事件管理單元 42.1.5. 軟件設(shè)計方法 62.2. MPPT的控制方法與參數(shù)計算 72.3. 同頻、同相的控制方法和參數(shù)計算 8
標簽： tms320f2812 光伏 并網(wǎng)發(fā)電 模擬 protel pcb
上傳時間： 2021-11-02
上傳用戶：
IIC接口E2PROM(AT24C64) 讀寫VERILOG 驅(qū)動源碼+仿真激勵文件:module i2c_dri #( parameter SLAVE_ADDR = 7'b1010000 , //EEPROM從機地址 parameter CLK_FREQ = 26'd50_000_000, //模塊輸入的時鐘頻率 parameter I2C_FREQ = 18'd250_000 //IIC_SCL的時鐘頻率 ) ( input clk , input rst_n , //i2c interface input i2c_exec , //I2C觸發(fā)執(zhí)行信號 input bit_ctrl , //字地址位控制(16b/8b) input i2c_rh_wl , //I2C讀寫控制信號 input [15:0] i2c_addr , //I2C器件內(nèi)地址 input [ 7:0] i2c_data_w , //I2C要寫的數(shù)據(jù) OUTPUT reg [ 7:0] i2c_data_r , //I2C讀出的數(shù)據(jù) OUTPUT reg i2c_done , //I2C一次操作完成 OUTPUT reg i2c_ack , //I2C應(yīng)答標志 0:應(yīng)答 1:未應(yīng)答 OUTPUT reg scl , //I2C的SCL時鐘信號 inout sda , //I2C的SDA信號 //user interface OUTPUT reg dri_clk //驅(qū)動I2C操作的驅(qū)動時鐘 );//localparam definelocalparam st_idle = 8'b0000_0001; //空閑狀態(tài)localparam st_sladdr = 8'b0000_0010; //發(fā)送器件地址(slave address)localparam st_addr16 = 8'b0000_0100; //發(fā)送16位字地址localparam st_addr8 = 8'b0000_1000; //發(fā)送8位字地址localparam st_data_wr = 8'b0001_0000; //寫數(shù)據(jù)(8 bit)localparam st_addr_rd = 8'b0010_0000; //發(fā)送器件地址讀localparam st_data_rd = 8'b0100_0000; //讀數(shù)據(jù)(8 bit)localparam st_stop = 8'b1000_0000; //結(jié)束I2C操作//reg definereg sda_dir ; //I2C數(shù)據(jù)(SDA)方向控制reg sda_out ; //SDA輸出信號reg st_done ; //狀態(tài)結(jié)束reg wr_flag ; //寫標志reg [ 6:0] cnt ; //計數(shù)reg [ 7:0] cur_state ; //狀態(tài)機當前狀態(tài)reg [ 7:0] next_state; //狀態(tài)機下一狀態(tài)reg [15:0] addr_t ; //地址reg [ 7:0] data_r ; //讀取的數(shù)據(jù)reg [ 7:0] data_wr_t ; //I2C需寫的數(shù)據(jù)的臨時寄存reg [ 9:0] clk_cnt ; //分頻時
標簽： iic 接口 e2prom at24c64 verilog 驅(qū)動 仿真
上傳時間： 2021-11-05
上傳用戶：
ABSTRACTThe flyback power stage is a popular choice for single and multiple OUTPUT dc-to-dc converters at powerlevels of 150 Watts or less. Without the OUTPUT inductor required in buck derived topologies, such as theforward or push-pull converter, the component count and cost are reduced. This application note will reviewthe design procedure for the power stage and control electronics of a flyback converter. In these isolatedconverters, the error signal from the secondary still needs to cross the isolation boundary to achieveregulation. By using the UC3965 Precision Reference with Low Offset Error Amplifier on the secondaryside to drive an optocoupler and the UCC3809 Economy Primary Side Controller on the primary side, asimple and low cost 50 Watt isolated power supply is realized.
標簽： 隔離
上傳時間： 2021-11-24
上傳用戶：kingwide
General Design Specification:1. AC Input Range 180-264Vac, Isolated ac-dc offline, 12LEDS,OUTPUT 700mA2. Intelligent wall dimmer detections(Leading-edge dimmer , Trailing-edgedimmer , No-dimmer)3. Multiple dimming control scheme4. Wide dimming range from 1% up to 100%5. No visible flicker6. Resonant control to achieve high efficiency7. High Power Factor, 0.9 without dimmer8. Temperature degrade control to adjust the LED9. Primary-only Sensing eliminates opto-isolator feedback and simplifies design
標簽： iw3617
上傳時間： 2021-12-03
上傳用戶：canderile
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