Batch version of the back-propagation algorithm. % Given a set of corresponding input-OUTPUT pairs and an initial network % [W1,W2,critvec,iter]=batbp(NetDef,W1,W2,PHI,Y,trparms) trains the % network with backpropagation. % % The activation functions must be either linear or tanh. The network % architecture is defined by the matrix NetDef consisting of two % rows. The first row specifies the hidden layer while the second % specifies the OUTPUT layer. %
標簽: back-propagation corresponding input-OUTPUT algorithm
上傳時間: 2016-12-27
上傳用戶:exxxds
Produces a matrix of derivatives of network OUTPUT w.r.t. % each network weight for use in the functions NNPRUNE and NNFPE.
標簽: network w.r.t. derivatives Produces
上傳時間: 2013-12-18
上傳用戶:sunjet
verilog code 4-bit carry look-ahead adder OUTPUT [3:0] s //summation OUTPUT cout //carryout input [3:0] i1 //input1 input [3:0] i2 //input2 input c0 //前一級進位
標簽: OUTPUT look-ahead summation carryout
上傳時間: 2017-01-07
上傳用戶:yyq123456789
verilog code 16-bit carry look-ahead adder OUTPUT [15:0] sum // 相加總和 OUTPUT carryout // 進位 input [15:0] A_in // 輸入A input [15:0] B_in // 輸入B input carryin // 第一級進位 C0
標簽: OUTPUT look-ahead carryout verilog
上傳時間: 2014-12-06
上傳用戶:ls530720646
verilog code array_multiplier OUTPUT [7:0] product input [3:0] wire_x input [3:0] wire_y
標簽: input array_multiplier verilog product
上傳時間: 2014-01-04
上傳用戶:wxhwjf
verilog code radix-2 SRT divider input [7:0]Dividend input [3:0]Divisor OUTPUT [4:0]Quotient OUTPUT [8:0]Remainder
標簽: input Dividend Quotient verilog
上傳時間: 2014-11-27
上傳用戶:三人用菜
編寫input()和OUTPUT()函數輸入,輸出5個學生的數據記錄,主要練習使用這兩個函數
上傳時間: 2017-01-17
上傳用戶:qoovoop
本例展示了如何設置TIM工作在輸出比較-非主動模式(OUTPUT Compare Inactive mode),并產生相應的中斷。 TIM2時鐘設置為36MHz,預分頻設置為35999,TIM2計數器時鐘可表達為: TIM2 counter clock = TIMxCLK / (Prescaler +1) = 1 KHz 設置TIM2_CCR1寄存器值為1000, CCR1寄存器值1000除以TIM2計數器時鐘頻率1KHz,為1000毫秒。因此,經過1000毫秒的時延,置PC.06輸出為低電平。 同理,根據寄存器TIM2_CCR2 、TIM2_CCR3和 TIM2_CCR4的值,經過500毫秒的時延,置PC.07輸出為低電平;經過250毫秒的時延,置PC.08輸出為低電平;經過125毫秒的時延,置PC.09輸出為低電平。 輸出比較寄存器的值決定時延的大小,當計數器的值小于這個值的時候,點亮與PC.06-PC.09相連的LED;當計數器的值達到這個值得時候,產生中斷,在TIM2的4個通道相應的中斷里,把它們一一關閉。
標簽: Inactive Compare OUTPUT mode
上傳時間: 2013-12-20
上傳用戶:ghostparker
OC0 OUTPUT mode 設定了pwm輸出控制選擇
上傳時間: 2013-12-26
上傳用戶:ynsnjs
Input : A set S of planar points OUTPUT : A convex hull for S Step 1: If S contains no more than five points, use exhaustive searching to find the convex hull and return. Step 2: Find a median line perpendicular to the X-axis which divides S into SL and SR SL lies to the left of SR . Step 3: Recursively construct convex hulls for SL and SR. Denote these convex hulls by Hull(SL) and Hull(SR) respectively. Step 4: Apply the merging procedure to merge Hull(SL) and Hull(SR) together to form a convex hull. Time complexity: T(n) = 2T(n/2) + O(n) = O(n log n)
標簽: contains OUTPUT convex planar
上傳時間: 2017-02-19
上傳用戶:wyc199288