<sup id="quaqo"></sup> <button id="quaqo"></button> 波長信號的解調是實現光纖光柵傳感網絡的關鍵，基于現有的光纖光柵傳感器解調方法，提出一種基于FPGA的雙匹配光纖光柵解調方法，此系統是一種高速率、高精度、低成本的解調系統，并且通過引入雙匹配光柵有效地克服了雙值問題同時擴大了檢測范圍。分析了光纖光柵的測溫原理并給出了該方案軟硬件設計，綜合考慮系統的解調精度和FPGA的處理速度給出了基于拉格朗日的曲線擬合算法。 Abstract: Sensor is one of the most important application of the fiber grating. Wavelength signal demodulating is the key techniques to carry out fiber grating sensing network， based on several existing methods of fiber grating sensor demodulation inadequate， a two-match fiber grating demodulation method was presented. This system is a high-speed， high precision， low-cost demodulation system. And by introducing a two-match grating effectively overcomes the problem of double value while expands the scope of testing. This Paper analyzes the principle of fiber Bragg grating temperature and gives the software and hardware design of the program. Considering the system of demodulation accuracy and processing speed of FPGA，this Paper gives the curve fitting algorithm based on Lagrange.
上傳時間： 2013-10-10
上傳用戶：zxc23456789
1.什么是CTP? CTP包括幾種含義: 脫機直接制版(Computer-to-plate) 在機直接制版(Computer-to-press) 直接印刷(Computer-to-Paper/print) 數字打樣(Computer-to-proof) 普通PS版直接制版技術,即CTcP(Computer-to-conventional plate) 這里所論述的CTP系統是脫機直接制版(Computer-to-plate)。CTP就是計算機直接到印版，是一種數字化印版成像過程。CTP直接制版機與照排機結構原理相仿。起制版設備均是用計算機直接控制，用激光掃描成像，再通過顯影、定影生成直接可上機印刷的印版。計算機直接制版是采用數字化工作流程，直接將文字、圖象轉變為數字，直接生成印版，省去了膠片這一材料、人工拼版的過程、半自動或全自動曬版工序。
標簽： CTP
上傳時間： 2014-01-22
上傳用戶：魚哥哥你好
本文利用Verilog HDL 語言自頂向下的設計方法設計多功能數字鐘，突出了其作為硬件描述語言的良好的可讀性、可移植性和易理解等優點，并通過Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成綜合、仿真。此程序通過下載到FPGA 芯片后，可應用于實際的數字鐘顯示中。 關鍵詞：Verilog HDL；硬件描述語言；FPGA Abstract: In this Paper, the process of designing multifunctional digital clock by the Verilog HDL top-down design method is presented, which has shown the readability, portability and easily understanding of Verilog HDL as a hard description language. Circuit synthesis and simulation are performed by Altera QuartusⅡ 4.1 and ModelSim SE 6.0. The program can be used in the truly digital clock display by downloading to the FPGA chip. Keywords: Verilog HDL；hardware description language；FPGA
上傳時間： 2013-11-10
上傳用戶：hz07104032
ref-sdr-sdram-vhdl代碼 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.
上傳時間： 2013-10-23
上傳用戶：半熟1994
The revolution of automation on factory floors is a key driver for the seemingly insatiable demand for higher productivity， lower total cost of ownership，and high safety. As a result， industrial applications drive an insatiable demand of higher data bandwidth and higher system-level performance. This white Paper describes the trends and challenges seen by designers and how FPGAs enable solutions to meet their stringent design goals.
上傳時間： 2013-11-08
上傳用戶：yan2267246
在Multisim 10軟件環境下，設計一種由運算放大器構成的精確可控矩形波信號發生器，結合系統電路原理圖重點闡述了各參數指標的實現與測試方法。通過改變RC電路的電容充、放電路徑和時間常數實現了占空比和頻率的調節，通過多路開關投入不同數值的電容實現了頻段的調節，通過電壓取樣和同相放大電路實現了輸出電壓幅值的調節并提高了電路的帶負載能力，可作為頻率和幅值可調的方波信號發生器。Multisim 10仿真分析及應用電路測試結果表明，電路性能指標達到了設計要求。 Abstract: Based on Multisim 10， this Paper designed a kind of rectangular-wave signal generator which could be controlled exactly composed of operational amplifier， the key point was how to implement and test the parameter indicators based on the circuit diagram. The duty and the frequency were adjusted by changing the time constant and the way of charging and discharging of the capacitor， the width of frequency was adjusted by using different capacitors provided with multiple switch， the amplitude of output voltage was adjusted by sampling voltage and using in-phase amplifier circuit，the ability of driving loads was raised， the circuit can be used as squarewave signal generator whose frequency and amplitude can be adjusted. The final simulation results of Multisim 10 and the tests of applicable circuit show that the performance indicators of the circuit meets the design requirements.
上傳時間： 2014-01-21
上傳用戶：shen007yue
結合均勻設計表和小邊經驗公式產生初始種群，使TSP應用遺傳算法能求出更優更快解，詳盡說明見Paper.doc。
上傳時間： 2013-12-24
上傳用戶：蟲蟲蟲蟲蟲蟲
The code assumes a two-dimensional computational domain with TMz polarization (i.e., non-zero field Ez, Hx, and Hy). The program is currently written so that the incident field always strikes the lower-left corner of the total-field region first. (If you want a different corner, that should be a fairly simple tweak to the code, but for now you ll have to make that tweak yourself.) I have attempted to provide copious comments in the code and hope that a knowledgeable C programmer can quickly map the approach as described in the Paper to what is in the program.
標簽： two-dimensional computational polarization non-zero
上傳時間： 2013-12-13
上傳用戶：cylnpy
The tar file contains the following files: ptfsf.c: heart of the perfect TFSF code ptfsf.h: header file for same ptfsf-demo.c: FDTD code which demonstrates use of perfect TFSF code. Essentially this program used to generate results shown in the Paper ptfsf-file-maker.c: code to generate an incident-field file using the "perfect" incident fields ptfsf-demo-file.c: FDTD code which uses the perfect incident fields stored in a file fdtdgen.h: defines macros used in much of my code Makefile: simple make-file to compile programs Also include are some simple script files to run the programs with reasonable values. The code assumes a two-dimensional computational domain with TMz polarization (i.e., non-zero field Ez, Hx, and Hy). The program is currently written so that the incident field always strikes the lower-left corner of the total-field region first. (If you want a different corner, that should be a fairly simple tweak to the code, but for now you ll have to make that tweak yourself.)
標簽： ptfsf following the contains
上傳時間： 2013-11-28
上傳用戶：風之驕子
This set of simulation files performs a computational complexity performance comparison of the two methods mentioned in the Paper. The source is ANSI-C compliant, hence any C-compiler can be used to compile the source code. It has been tested using Visual Studio.net C++ and TI code composer studio C compiler for the TMS320C6701. Note that the performance comparison may be different for different platforms.
標簽： computational performance complexity comparison
上傳時間： 2014-12-22
上傳用戶：aig85
