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The STWD100 watchdog timer circuits are self-contained devices which prevent systemfailures that are caused by certain types of hardware errors (non-responding peripherals,bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.).The STWD100 watchdog timer has an input, WDI, and an output, WDO (see Figure 2). Theinput is used to clear the internal watchdog timer periodically within the specified timeoutperiod, twd (see SECTION 3: Watchdog timing). While the system is operating correctly, itperiodically toggles the watchdog input, WDI. If the system fails, the watchdog timer is notreset, a system alert is generated and the watchdog output, WDO, is asserted (seeSECTION 3: Watchdog timing).The STWD100 circuit also has an enable pin, EN (see Figure 2), which can enable ordisable the watchdog functionality. The EN pin is connected to the internal pull-downresistor. The device is enabled if the EN pin is left floating.
標(biāo)簽：
3.3
看門狗
芯片
上傳時(shí)間：
2013-10-22
上傳用戶：taiyang250072
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This overview guide describes all the peripherals available for TMS320x28xx and TMS320x28xxx devices.SECTION 2 shows the peripherals used by each device. SECTION 3 provides descriptions of the peripherals.You can download the peripheral guide by clicking on the literature number, which is linked to the portable document format (pdf) file.
標(biāo)簽：
281x
Dsp
281
外設(shè)
上傳時(shí)間：
2013-11-21
上傳用戶：HGH77P99
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The CodeWarrior Development Suite provides access and technical support to amultitude of CodeWarrior products. In this quick start guide, SECTION 1 explains howto register your CodeWarrior Development Suite. SECTION 2 explains how to activateand install one of your products. SECTION 3 describes what you are entitled to withthe purchase of your CodeWarrior Development Suite, and SECTION 4 discusses theavailable purchase options. SECTION 5 describes the benefits of maintaining a currenttechnical support contract, and SECTION 6 tells you how to access support.
標(biāo)簽：
CodeWarrior
開發(fā)套件
上傳時(shí)間：
2014-03-02
上傳用戶：784533221
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Abstract: This application note helps system designers choose the correct external components for use with the MAX16948 dualremote antenna LDO/switch, thus ensuring that automobile-regulated phantom antenna supply and output-current-monitoring circuitrymeet performance objectives. An electronic calculator is provided that helps specify the critical external components for theMAX16948, thus reducing design time. The calculator also determines the device's analog output voltage, output current-limitthreshold, and output current-sensing accuracies. The calculator includes new automatic Step By Step feature that assists designerswith component choice. To use the new automatic feature, click on the Step By Step button relative to the desired SECTION.
標(biāo)簽：
16948
MAX
LDO
遙控天線
上傳時(shí)間：
2013-11-04
上傳用戶：lhll918
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This application note shows how a Xilinx CoolRunnerTM-II CPLD can be used as a simplelogical switch that can quickly and reliably select between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the “VHDLCode” SECTION. The code can be expanded by the user to perform additional operations usingthe remaining CPLD resources
標(biāo)簽：
CoolRunner-II
Xilinx
XAPP
CPLD
上傳時(shí)間：
2013-12-16
上傳用戶：qwer0574
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This document provides practical, common guidelines for incorporating PCI Express interconnect
layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10-
layer or more server baseboard designs. Guidelines and constraints in this document are intended
for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI
Express devices located on the same baseboard (chip-to-chip routing) and interconnects between
a PCI Express device located “down” on the baseboard and a device located “up” on an add-in
card attached through a connector.
This document is intended to cover all major components of the physical interconnect including
design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card
edge-finger and connector considerations. The intent of the guidelines and examples is to help
ensure that good high-speed signal design practices are used and that the timing/jitter and
loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect.
However, while general physical guidelines and suggestions are given, they may not necessarily
guarantee adequate performance of the interconnect for all layouts and implementations.
Therefore, designers should consider modeling and simulation of the interconnect in order to
ensure compliance to all applicable specifications.
The document is composed of two main SECTIONs. The first SECTION provides an overview of
general topology and interconnect guidelines. The second SECTION concentrates on physical layout
constraints where bulleted items at the beginning of a topic highlight important constraints, while
the narrative that follows offers additional insight.
標(biāo)簽：
pci
PCB
設(shè)計(jì)規(guī)范
上傳時(shí)間：
2014-01-24
上傳用戶：s363994250
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PE可執(zhí)行文件的鑲?cè)胧匠绦虻木帉懛椒笆纠?鑲?cè)胧胶箝T程序&原程序) 由于Microsoft公司的Windows系統(tǒng)是當(dāng)前大部分個(gè)人電腦所使用的操作系統(tǒng) 主要包括win95,98,me,nt4,2000,xp等，而這些系統(tǒng)所使用的可執(zhí)行文件的格式基 本上是PE結(jié)構(gòu)的。這里的可執(zhí)行文件的鑲?cè)胧匠绦蚓褪轻槍?duì)PE結(jié)構(gòu)的可執(zhí)行文件。 這里先簡(jiǎn)單說一下PE文件框架結(jié)構(gòu)： DOS MZ header DOS stub//在不支持 PE文件格式的操作系統(tǒng)中它將簡(jiǎn)單顯示一個(gè)錯(cuò)誤提示 PE header//含了許多PE裝載器用到的重要信息 SECTION table//每個(gè)SECTION的信息 SECTION 1 SECTION 2 SECTION 3.... 由于SECTIONAlignment 塊對(duì)齊的原因每個(gè)SECTION之間都會(huì)產(chǎn)生很多空間， 鑲?cè)胧匠绦虻拇a可以放在SECTION之間的空位上，比較方便的方法是把代碼放在 最后一個(gè)SECTION的末尾，然后更改Misc.VirtualSize和SizeOfRawData這兩個(gè)位 于SECTION table的IMAGE_SECTION_HEADER結(jié)構(gòu)數(shù)組的成員。如果代碼十分的長(zhǎng)， 有時(shí)候會(huì)造成鑲?cè)氲拇a無法被完全加載而產(chǎn)生錯(cuò)誤，這時(shí)需要更改SizeOfImage 在IMAGE_NT_HEADERS 結(jié)構(gòu)中。 在不同的WINDOWS版本中api調(diào)用地址也有不同，為了解決這個(gè)問題可以更改引 入表讓加載器
標(biāo)簽：
Microsoft
Windows
程序
200
上傳時(shí)間：
2015-01-13
上傳用戶：luopoguixiong
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Copyright© 2004 Sergiu Dumitriu, Marta Gî rdea, Că tă lin Hriţ cu Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation with no Invariant SECTIONs, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the SECTION entitled "GNU Free Documentation License" All brand names, product names, or trademarks belong to their respective holders.
標(biāo)簽：
Permission
Copyright
259
Dumitriu
上傳時(shí)間：
2015-04-02
上傳用戶：jackgao
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jboss 開發(fā)人員 手冊(cè)
JBoss: A Developer s Notebook also introduces the management console, the web services messaging features, enhanced monitoring capabilities, and shows you how to improve performance. At the end of each lab, you ll find a SECTION called "What about..." that anticipates and answers likely follow-up questions, along with a SECTION that points you to articles and other resources if you need more information.
標(biāo)簽：
introduces
management
Developer
the
上傳時(shí)間：
2015-04-17
上傳用戶：dreamboy36
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VHDL 關(guān)于2DFFT設(shè)計(jì)程序
u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be
seen in the following SECTION.
u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus
network, and it support these sub-modules scinode1∼ scinode9 reset and clk
and global_cnt signals to synchronous the sub-modules to simplify the overall
design.
u proj2.wfc: VSS simulation result that is the same as the ModelSim simulation
result.
u Pro2_2.wfc: VSS simulation result of another test pattern can’t cause overflow
situation.
標(biāo)簽：
scinode1
scinode
details
2DFFT
上傳時(shí)間：
2014-12-02
上傳用戶：15071087253
