In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
標(biāo)簽： Efficient Verilog Digital Coding
上傳時間： 2013-11-22
上傳用戶：han_zh
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
標(biāo)簽： Efficient Verilog Digital Coding
上傳時間： 2013-11-23
上傳用戶：我干你啊
本文利用Verilog HDL 語言自頂向下的設(shè)計(jì)方法設(shè)計(jì)多功能數(shù)字鐘，突出了其作為硬件描述語言的良好的可讀性、可移植性和易理解等優(yōu)點(diǎn)，并通過Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成綜合、仿真。此程序通過下載到FPGA 芯片后，可應(yīng)用于實(shí)際的數(shù)字鐘顯示中。 關(guān)鍵詞：Verilog HDL；硬件描述語言；FPGA Abstract: In this paper, the process of designing multifunctional digital clock by the Verilog HDL top-down design method is presented, which has shown the readability, portability and easily understanding of Verilog HDL as a hard description language. Circuit synthesis and simulation are performed by Altera QuartusⅡ 4.1 and ModelSim SE 6.0. The program can be used in the truly digital clock display by downloading to the FPGA chip. Keywords: Verilog HDL；hardware description language；FPGA
標(biāo)簽： Verilog HDL 多功能 數(shù)字
上傳時間： 2013-11-10
上傳用戶：hz07104032
Verilog and VHDL狀態(tài)機(jī)設(shè)計(jì)，英文pdf格式 State machine design techniques for Verilog and VHDL Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding presented. Different methodologies will be compared using real-world examples.
標(biāo)簽： Verilog VHDL and 狀態(tài)
上傳時間： 2013-12-19
上傳用戶：change0329
用verilog設(shè)計(jì)密勒解碼器 一、題目： 設(shè)計(jì)一個密勒解碼器電路 二、輸入信號： 1． DIN：輸入數(shù)據(jù) 2． CLK：頻率為2MHz的方波，占空比為50％ 3． RESET：復(fù)位信號，低有效 三、輸入信號說明： 輸入數(shù)據(jù)為串行改進(jìn)密勒碼，每個碼元持續(xù)時間為8μs，即16個CLK時鐘；數(shù)據(jù)流是由A、B、C三種信號組成； A：前8個時鐘保持“1”，接著5個時鐘變?yōu)椤?”，最后3個時鐘為“1”。 B：在整個碼元持續(xù)時間內(nèi)都沒有出現(xiàn)“0”，即連續(xù)16個時鐘保持“1”。 C：前5個時鐘保持“0”，后面11個時鐘保持“1”。 改進(jìn)密勒碼編碼規(guī)則如下： 如果碼元為邏輯“1”，用A信號表示。 如果碼元為邏輯“0”，用B信號表示，但以下兩種特例除外：如果出現(xiàn)兩個以上連“0”，則從第二個“0”起用C信號表示；如果在“通信起始位”之后第一位就是“0”，則用C信號表示，以下類推； “通信起始位”，用C信號表示； “通信結(jié)束位”，用“0”及緊隨其后的B信號表示。 “無數(shù)據(jù)”，用連續(xù)的B信號表示。
標(biāo)簽： verilog 2MHz DIN CLK
上傳時間： 2013-12-02
上傳用戶：wang0123456789
本文：采用了FPGA方法來模擬高動態(tài)(Global Position System GPS)信號源中的C／A碼產(chǎn)生器。C／A碼在GPS中實(shí)現(xiàn)分址、衛(wèi)星信號粗捕和精碼(P碼)引導(dǎo)捕獲起著重要的作用，通過硬件描述語言VERILOG在ISE中實(shí)現(xiàn)電路生成，采用MODELSIM、SYNPLIFY工具分別進(jìn)行仿真和綜合。
標(biāo)簽： GPS Position Global System
上傳時間： 2015-12-01
上傳用戶：李彥東
PCI設(shè)計(jì)指南The Xilinx LogiCORE PCI interface is a fully verified, pre-implemented PCI Bus interface. This interface is available in 32-bit and 64- bit versions, with support for multiple Xilinx FPGA device families. It is designed to support both Verilog-HDL and VHDL. The design examples in this book are provided in Verilog.
標(biāo)簽： interface PCI pre-implemented LogiCORE
上傳時間： 2016-04-03
上傳用戶：清風(fēng)冷雨
Cores are generated from Confluence a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C
標(biāo)簽： Confluence generated language design
上傳時間： 2016-06-19
上傳用戶：h886166
用Verilog HDL編寫的0832源程序，實(shí)現(xiàn)對0832實(shí)現(xiàn)D/A轉(zhuǎn)換。也可方便地轉(zhuǎn)換為vhdl源程序。
上傳時間： 2013-11-25
上傳用戶：qiao8960
crc_table.c is for reset seed( 0000 ) crc_table_1.c is for reset seed( ffff) CRC16_D8_m.v is a verilog module of byte paralle crc. CRC16_D8_m_tb.v is the testbench file of above module.
標(biāo)簽： crc_table reset seed for
上傳時間： 2014-01-09
上傳用戶：181992417
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