Electrostatic discharge (ESD) is one of the most prevalent threats to the reliability of electronic components. It is an event in which a finite amount of charge is trans- ferred from one object (i.e., human body) to another (i.e., microchip). This process can result in a very high current passing through the microchip within a very short period of time, and, hence, more than 35% of chip damages can be attributed to an ESD-related event. As such, designing on-chip ESD structures to protect integrated circuits against the ESD stresses is a high priority in the semiconductor industry.
標簽： Electrostatic Protection Discharge
上傳時間： 2020-06-05
上傳用戶：shancjb
The goal of this book is to introduce the simulation methods necessary to describe the behaviour of semiconductor devices during an electrostatic discharge (ESD). The challenge of this task is the correct description of semiconductor devices under very high current density and high temperature transients. As it stands, the book can be no more than a snapshot and a summary of the research in this field during the past few years. The authors hope that the book will provide the basis for further development of simulation methods at this current frontier of device physics.
標簽： Development Protection ESD
上傳時間： 2020-06-05
上傳用戶：shancjb
The challenges associated with the design and implementation of Electro- static Discharge (ESD) protection circuits become increasingly complex as technology is scaled well into nano-metric regime. One must understand the behavior of semiconductor devices under very high current densities, high temperature transients in order to surmount the nano-meter ESD challenge. As a consequence, the quest for suitable ESD solution in a given technology must start from the device level. Traditional approaches of ESD design may not be adequate as the ESD damages occur at successively lower voltages in nano-metric dimensions.
標簽： Protection Circuit Device Design ESD and
上傳時間： 2020-06-05
上傳用戶：shancjb
Guideline Suggestion for High-Speed I/O ESD Protection
標簽： ESD_Suggestion_for_HighSpeed_IO_K er
上傳時間： 2020-06-05
上傳用戶：shancjb
Resource allocation is an important issue in wireless communication networks. In recent decades, cognitive radio technology and cognitive radio-based networks have obtained more and more attention and have been well studied to improve spectrum utilization and to overcomethe problem of spectrum scarcity in future wireless com- munication systems. Many new challenges on resource allocation appear in cogni- tive radio-based networks. In this book, we focus on effective solutions to resource allocation in several important cognitive radio-based networks, including a cogni- tive radio-basedopportunisticspectrum access network, a cognitiveradio-basedcen- tralized network, a cognitive radio-based cellular network, a cognitive radio-based high-speed vehicle network, and a cognitive radio-based smart grid.
上傳時間： 2020-06-07
上傳用戶：shancjb
Sound is simply an airborne version of vibration. The air which carries sound is a mixture of gases. In gases, the molecules contain so much energy that they break free from their neighbors and rush around at high speed. As Figure 1.1(a) shows, the innumerable elastic collisions of these high-speed molecules produce pressure on the walls of any gas container. If left undisturbed in a container at a constant temperature, eventually the pressure throughout would be constant and uniform.
標簽： Engineering Audio
上傳時間： 2020-06-09
上傳用戶：shancjb
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上傳時間： 2021-10-22
上傳用戶：
STM32L053C8T6數據手冊Features ? Ultra-low-power platform – 1.65 V to 3.6 V power supply – -40 to 125 °C temperature range – 0.27 μA Standby mode (2 wakeup pins) – 0.4 μA Stop mode (16 wakeup lines) – 0.8 μA Stop mode + RTC + 8 KB RAM retention – 139 μA/MHz Run mode at 32 MHz – 3.5 μs wakeup time (from RAM) – 5 μs wakeup time (from Flash) ? Core: ARM? 32-bit Cortex?-M0+ with MPU – From 32 kHz up to 32 MHz max. – 0.95 DMIPS/MHz ? Reset and supply management – Ultra-safe, low-power BOR (brownout reset) with 5 selectable thresholds – Ultralow power POR/PDR – Programmable voltage detector (PVD) ? Clock sources – 1 to 25 MHz crystal oscillator – 32 kHz oscillator for RTC with calibration – High speed internal 16 MHz factory-trimmed RC (+/- 1%) – Internal low-power 37 kHz RC – Internal multispeed low-power 65 kHz to 4.2 MHz RC – PLL for CPU clock ? Pre-programmed bootloader – USART, SPI supported ? Development support – Serial wire debug supported ? Up to 51 fast I/Os (45 I/Os 5V tolerant) ? Memories – Up to 64 KB Flash with ECC – 8KB RAM – 2 KB of data EEPROM with ECC – 20-byte backup register
標簽： stm32l053c8t6
上傳時間： 2022-02-06
上傳用戶：
ADC模數轉換器件Altium Designer AD原理圖庫元件庫SV text has been written to file : 4.4 - ADC模數轉換器件.csvLibrary Component Count : 29Name Description----------------------------------------------------------------------------------------------------ADC0800 National 8-Bit Analog to Digital ConverterADC0809 ADC0831 ADCADC0832 ADC8 Generic 8-Bit A/D ConverterCLC532 High-Speed 2:1 Analog MultiplexerCS5511 National 16-Bit Analog to Digital ConverterDAC8 Generic 8-Bit D/A ConverterEL1501 Differential line Driver/ReceiverEL2082 Current-Mode MultiplierEL4083 Current Mode Four Quadrant MultiplierEL4089 DC Restored Video AmplifierEL4094 Video Gain Control/FaderEL4095 Video Gain Contol/Fader/MultiplexerICL7106 LMC6953_NSC PCI Local Bus Power SupervisorMAX4147 300MHz, Low-Power, High-Output-Current, Differential Line DriverMAX4158 350MHz 2-Channel Video Multiplexer-AmplifierMAX4159 350MHz 2-Channel Video Multiplexer-AmplifierMAX4258 250MHz, 2-Channel Video Multiplexer-AmplifierMAX4259 250MHz 2-Channel Video Multiplexer-AmplifierMAX951 Ultra-Low-Power, Single-Supply Op Amp + Comparator + ReferenceMAX952 Ultra-Low-Power, Single-Supply Op Amp + Comparator + ReferenceMC1496 Balanced Modulator/DemodulatorPLL100k Generic Phase Locked LoopPLL10k Generic Phase Locked LoopPLL5k Generic Phase Locked LoopPLLx Generic Phase Locked Loop水位計
標簽： adc 模數轉換 altium designer
上傳時間： 2022-03-13
上傳用戶：
基于FPGA設計的相關論文資料大全 84篇用FPGA實現FFT的研究 劉朝暉 韓月秋 摘 要 目的 針對高速數字信號處理的要求，給出了用現場可編程門陣列(FPGA)實現的 快速傅里葉變換(FFT)方案.方法 算法為按時間抽取的基4算法，采用遞歸結構的塊浮點運 算方案，蝶算過程只擴展兩個符號位以適應雷達信號處理的特點，乘法器由陣列乘法器實 現.結果 采用流水方式保證系統的速度，使取數據、計算旋轉因子、復乘、DFT等操作協 調一致，在計算、通信和存儲間取得平衡，避免了瓶頸的出現.結論 實驗表明，用FPGA 實現高速數字信號處理的算法是一個可行的方案. 關鍵詞 離散傅里葉變換； 快速傅里葉變換； 塊浮點運算； 可編程門陣列 分類號 TP39； TN957.511 Implementation of FFT with FPGA Technology Liu Zhaohui Han Yueqiu (Department of Electronics Engineering, Beijing Institute of Technology, Beijing 100081) Abstract Aim To propose a scheme for implementing FFT with FPGA in accor-dance with the requirement for high speed digital signal processing. Methods The structure of FPGA and requirement of system were considered in the experiment, radix-4 algorithm of DIT and recursive structure were adopted. The group float point arithmetic operation was used in the butterfly and the array multiplier was used to realize multiplication. Results The pipeline pattern was used to ensure the system speed, it made fetching data, calculating twiddle factor, complex multiplication and D
標簽： fpga
上傳時間： 2022-03-23
上傳用戶：
