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Xilinx-XUPV

基于Xilinx+FPGA的OFDM通信系統基帶設計-程序

《基于Xilinx FPGA的OFDM通信系統基帶設計》附帶的代碼

標簽： Xilinx FPGA OFDM 通信系統

上傳時間： 2013-12-21

上傳用戶：王慶才
Xilinx-Spartan6 FPGA實現MultiBoot

通過Xilinx Spartan-6 FPGA 的Multiboot特性,允許用戶一次將多個配置文件下載入Flash中,根據不同時刻的需求,在不掉電重啟的情況下,從中選擇一個來重配置FPGA,實現不同功能,提高器件利用率,增加系統安全性,降低系統成本。

標簽： Xilinx-Spartan MultiBoot FPGA

上傳時間： 2013-10-26

上傳用戶：wpwpwlxwlx
WP374 Xilinx FPGA的部分重配置

WP374 Xilinx FPGA的部分重配置

標簽： Xilinx FPGA 374 WP

上傳時間： 2013-11-03

上傳用戶：文993
XAPP503-針對Xilinx器件的SVF和XSVF文件格式

This application note provides users with a general understanding of the SVF and XSVF fileformats as they apply to Xilinx devices. Some familiarity with IEEE STD 1149.1 (JTAG) isassumed. For information on using Serial Vector Format (SVF) and Xilinx Serial Vector Format(XSVF) files in embedded programming applications

標簽： Xilinx XAPP XSVF 503

上傳時間： 2015-01-02

上傳用戶：時代將軍
XAPP944 - 將Xilinx CoolRunner-II CPLD用作數據流開關

This application note shows how a Xilinx CoolRunnerTM-II CPLD can be used as a simplelogical switch that can quickly and reliably select between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the “VHDLCode” section. The code can be expanded by the user to perform additional operations usingthe remaining CPLD resources

標簽： CoolRunner-II Xilinx XAPP CPLD

上傳時間： 2013-12-16

上傳用戶：qwer0574
WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮點DSP算法實現方案

WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮點DSP算法實現方案： High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs

標簽： Xilinx FPGA 409 DSP

上傳時間： 2013-10-21

上傳用戶：huql11633
基于Xilinx FPGA的雙輸出DC/DC轉換器解決方案

Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.

標簽： Xilinx FPGA DC 輸出

上傳時間： 2013-10-22

上傳用戶：aeiouetla
WP312-Xilinx新一代28nm FPGA技術簡介

Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.

標簽： Xilinx FPGA 312 WP

上傳時間： 2013-12-07

上傳用戶：bruce
xilinx Zynq-7000 EPP產品簡介

The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.

標簽： xilinx Zynq 7000 EPP

上傳時間： 2013-10-09

上傳用戶：evil
XAPP058 -利用嵌入式微控制器實現Xilinx系統編程

Xilinx 高性能 CPLD、FPGA 和配置 PROM 系列具備在系統可編程性、可靠的引腳鎖定以及JTAG 邊界掃描測試功能。此強大的功能組合允許設計人員在進行重大更改時，仍能保留原始的器件引腳，從而避免重組 PC 板。通過利用嵌入式控制器從板載 RAM 或 EPROM 對這些CPLD 和 FPGA 編程，設計人員可輕松升級、修改和測試設計，即使在現場也是如此。

標簽： Xilinx XAPP 058 嵌入式

上傳時間： 2013-11-03

上傳用戶：dongbaobao

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