一篇關(guān)于TCP-Vegas的文獻:Vegas is an implementation of TCP that achieves between 37 and 71％ better throughput on the Internet, with onefifth to one-half the losses, as compared to the implementation of TCP in the Reno distribution of BSD Unix. This paper motivates and describes the three key techniques employed by Vegas, and presents the results of a comprehensive experimental performance study—using both simulations and measurements on the Internet—of the Vegas and Reno implementations of TCP.
標簽： implementation TCP-Vegas throughpu achieves
上傳時間： 2014-01-08
上傳用戶：lwwhust
The MAX2691 low-noise amplifier (LNA) is designed forGPS L2 applications. Designed in Maxim’s advancedSiGe process, the device achieves high gain andlow noise figure while maximizing the input-referred 1dBcompression point and the 3rd-order intercept point. TheMAX2691 provides a high gain of 17.5dB and sub 1dBnoise figure.
標簽： Amplifier Low-Noise 2691 Band
上傳時間： 2014-12-04
上傳用戶：zaocan888
OPTOELECTRONICS CIRCUIT COLLECTION AVALANCHE PHOTODIODE BIAS SUPPLY 1Provides an output voltage of 0V to +80V for reverse biasingan avalanche photodiode to control its gain. This circuit canalso be reconfigured to supply a 0V to –80V output.LINEAR TEC DRIVER–1This is a bridge-tied load (BTL) linear amplifier for drivinga thermoelectric cooler (TEC). It operates on a single +5Vsupply and can drive ±2A into a common TEC.LINEAR TEC DRIVER–2This is very similar to DRIVER–1 but its power output stagewas modified to operate from a single +3.3V supply in orderto increase its efficiency. Driving this amplifier from astandard +2.5V referenced signal causes the output transistorsto have unequal power dissipation.LINEAR TEC DRIVER–3This BTL TEC driver power output stage achieves very highefficiency by swinging very close to its supply rails, ±2.5V.This driver can also drive ±2A into a common TEC. Operationis shown with the power output stage operating on±1.5V supplies. Under these conditions, this linear amplifiercan achieve very high efficiency. Application ReportThe following collection of analog circuits may be useful in electro-optics applications such as optical networkingsystems. This page summarizes their salient characteristics.
標簽： 光電轉(zhuǎn)換 電路設(shè)計
上傳時間： 2013-10-27
上傳用戶：落花無痕
以C8051F020為核心處理器，設(shè)計無線傳感器網(wǎng)絡(luò)數(shù)據(jù)采集系統(tǒng)。系統(tǒng)采用SZ05-ADV型無線通訊模塊組建Zigbee無線網(wǎng)絡(luò)，結(jié)合嵌入式系統(tǒng)的軟硬件技術(shù)，完成終端節(jié)點的8路傳感器信號的數(shù)據(jù)采集?，F(xiàn)場8路信號通過前端處理后，分別送入C8051F020的12位A/D轉(zhuǎn)換器進行轉(zhuǎn)換。經(jīng)過精確處理、存儲后的現(xiàn)場數(shù)據(jù)，通過Zigbee無線網(wǎng)絡(luò)傳送到上位機，系統(tǒng)可達到汽車試驗中無線測試的目的。 Abstract: This paper designs a wireless sensor network system for data acquisition with C8051F020 as core processors.The system used SZ05-ADV wireless communication module，set up a Zigbee wireless network， combined with hardware and software technologies of embedded systems，completed the end-node 8-locale sensor signal data acquisition.Eight locale signals were sent separately into the 12-bit ADC of C8051F020 for conversion through front treatment.After accurate processing and storage，the locale data was transmitted to the host computer through Zigbee wireless.The system achieves the purpose of wireless testing in vehicle trial.
標簽： C8051F020 Zigbee 汽車測試 系統(tǒng)設(shè)計
上傳時間： 2013-11-23
上傳用戶：dsgkjgkjg
為提高溫度測量效率，降低系統(tǒng)的成本，擴展傳輸距離，設(shè)計出一種新型溫度采集系統(tǒng)。單片機通過控制具有單總線方式的溫度傳感器DS18B20實現(xiàn)對溫度的測量，同時單片機通過控制具有單總線方式300～450MHz頻率范圍內(nèi)的MAX7044與MAX7033無線發(fā)射與接收芯片實現(xiàn)溫度數(shù)據(jù)的無線傳輸。與傳統(tǒng)溫度采集系統(tǒng)相比，該系統(tǒng)利用單總線方式連接，采用無線傳輸方式實現(xiàn)遠距離通信，易于系統(tǒng)的集成與擴展。實驗結(jié)果表明，該系統(tǒng)結(jié)構(gòu)簡單、方便移植，能夠同時實現(xiàn)多達上百點溫度的測量與500m范圍的傳輸。 Abstract: To improve the temperature measurement efficiency and reduce system cost,expansion of transmission distance,a new type of temperature acquisition system is designed.Microcontroller controlled temperature sensor DS18B20which has a single-bus achieves temperature measurement,while microcontroller by controlled the MAX7044and MAX7033chip with a single-bus and having300~450MHz radiofrequency to achieve the wireless transmission of temperature data.Compared with conventional temperature acquisition system,the system uses single-bus connected,and uses wireless transmission means to achieve long-distance communications,easy-to-system integration and expansion.The experimental results show that the system is simple,convenient transplantation,and can be implemented in as many as a hundred-point temperature measure-ment and the transmission range of500meters.
標簽： 單總線 無線溫度 采集 系統(tǒng)設(shè)計
上傳時間： 2013-10-29
上傳用戶：515414293
以89S52單片機和EP1C6Q240C8型FPGA為控制核心的多功能計數(shù)器，是由峰值檢波、A/D轉(zhuǎn)換、程控放大、比較整形、移相網(wǎng)絡(luò)部分組成,可實現(xiàn)測量正弦信號的頻率、周期和相位差的功能。多功能計數(shù)器采用等精度的測量方法，可實現(xiàn)頻率為1Hz～10MHz、幅度為0.01～5Vrms的正弦信號的精確測頻，以及頻率為10Hz～100kHz、幅度為0.5～5Vrms的正弦信號精確測相。液晶顯示器能夠?qū)崟r顯示當前信號的頻率、周期和相位差。該多功能計數(shù)器精度高，界面友好，實用性強。 Abstract: A multi-function counter，which uses89S52MCU and EP1C6Q240C8FPGA as a control core，consists of peak detector，A/D conversion，program-controlled amplification，compared shaping and phase-shifting network part.The counter measures the frequency，period and phase of sinusoidal signal.With the equal precision method,the multi-function counter achieves the precise frequency measurement of the sinusoidal signal which its frequency is from1Hz to10MHz，its amplitude is from0.01Vrms to5Vrms，as well as the accurate phase measurement of the sinusoidal signal which its frequency is from10Hz to100kHz，its amplitude is from0.5Vrms to5Vrms.The LCD monitor real-time displays the frequency，period and phase difference of current signal.The multi-function counter features high precision，friendly interface，and strong practical.
上傳時間： 2013-11-15
上傳用戶：gy592333
基于幅移鍵控技術(shù)ASK（Amplitude-Shift Keying），以C8051F340單片機作為監(jiān)測終端控制器，C8051F330D單片機作為探測節(jié)點控制器，采用半雙工的通信方式，通過監(jiān)控終端和探測節(jié)點的無線收發(fā)電路，實現(xiàn)數(shù)據(jù)的雙向無線傳輸。收發(fā)電路采用直徑為0.8 mm的漆包線自行繞制成圓形空心線圈天線，天線直徑為（3.4±0.3）cm。試驗表明，探測節(jié)點與監(jiān)測終端的通信距離為24 cm，通過橋接方式，節(jié)點收發(fā)功率為102 mW時，節(jié)點間的通信距離可達20 cm。與傳統(tǒng)無線收發(fā)模塊相比，該無線收發(fā)電路在受體積、功耗、成本限制的場合有廣闊的應(yīng)用前景。 Abstract: Based on ASK technology and with the C8051F340 and C8051F330D MCU as the controller， using half-duplex communication mode， this paper achieves bi-directional data transfer. Transceiver circuit constituted by enameled wire which diameter is 0.8mm and wound into a diameter （3.4±0.3） cm circular hollow coil antenna. Tests show that the communication distance between detection and monitoring of the terminal is 24cm，the distance is up to 20cm between two nodes when using the manner of bridging and the node transceiver power is 102mW. Compared with the conventional wireless transceiver modules， the circuit has wide application prospect in small size， low cost and low power consumption and other characteristics.
標簽： C8051F 單片機 無線收發(fā) 電路設(shè)計
上傳時間： 2013-10-19
上傳用戶：xz85592677
為了擴大監(jiān)控范圍，提高資源利用率，降低系統(tǒng)成本，提出了一種多通道視頻切換的解決方案。首先從視頻信號分離出行場信號，然后根據(jù)行場信號由DSP和FPGA產(chǎn)生控制信號，控制多路視頻通道之間的切換，從而實現(xiàn)讓一個視頻處理器同時監(jiān)控不同場景。實驗結(jié)果表明，該方案可以在視頻監(jiān)控告警系統(tǒng)中穩(wěn)定、可靠地實現(xiàn)視頻通道的切換。 Abstract: To expand the scope of monitoring， improve resource utilization， reduce system cost， a multiple video channels signal switching method is pointed out in this paper. First， horizontal sync signal and field sync signal from the video signal are separated， then control signal according to the sync signal by DSP and FPGA is generated to control the switching between multiple video channels. Thus， it achieves to make a video processor to monitor different place. Experimental results show that the method can realize video channel switching reliably， and is applied in the video monitoring warning system successfully.
上傳時間： 2013-11-09
上傳用戶：不懂夜的黑
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構(gòu)
上傳時間： 2013-11-13
上傳用戶：瓦力瓦力hong
為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對移相（QDPSK)信號調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺上，進行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達到了預(yù)期的設(shè)計要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標簽： QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計
上傳時間： 2014-01-13
上傳用戶：qoovoop
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