中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-21
上傳用戶：wxqman
為了在CDMA系統中更好地應用QDPSK數字調制方式，在分析四相相對移相（QDPSK)信號調制解調原理的基礎上，設計了一種QDPSK調制解調電路，它包括串并轉換、差分編碼、四相載波產生和選相、相干解調、差分譯碼和并串轉換電路。在MAX+PLUSⅡ軟件平臺上，進行了編譯和波形仿真。綜合后下載到復雜可編程邏輯器件EPM7128SLC84-15中，測試結果表明，調制電路能正確選相，解調電路輸出數據與QDPSK調制輸入數據完全一致，達到了預期的設計要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
上傳時間： 2013-10-28
上傳用戶：jyycc
關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標簽： investigates implementing pipelines circuits
上傳時間： 2015-07-26
上傳用戶：CHINA526
TMidiGen is a MIDI component by Alan Warriner which allows the simple creation of sound effects and note sequences within an application without the need for external files or resources. TMidiGen achieves this by generating the MIDI data in memory.
標簽： component TMidiGen Warriner creation
上傳時間： 2016-10-25
上傳用戶：h886166
DDR SDRAM控制器的VHDL源代碼，含詳細設計文檔。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上傳時間： 2014-11-01
上傳用戶：l254587896
The combinatorial core of the OVSF code assignment problem that arises in UMTS is to assign some nodes of a complete binary tree of height h (the code tree) to n simultaneous connections, such that no two assigned nodes (codes) are on the same root-to-leaf path. Each connection requires a code on a specified level. The code can change over time as long as it is still on the same level. We consider the one-step code assignment problem: Given an assignment, move the minimum number of codes to serve a new request. Minn and Siu proposed the so-called DCAalgorithm to solve the problem optimally. We show that DCA does not always return an optimal solution, and that the problem is NP-hard. We give an exact nO(h)-time algorithm, and a polynomial time greedy algorithm that achieves approximation ratio Θ(h). Finally, we consider the online code assignment problem for which we derive several results
標簽： combinatorial assignment problem arises
上傳時間： 2014-01-19
上傳用戶：BIBI
MPI stands for the Message Passing Interface. Written by the MPI Forum (a large committee comprising of a cross-section between industry and research representatives), MPI is a standardized API typically used for parallel and/or distributed computing. The MPI standard is comprised of 2 documents: MPI-1 (published in 1994) and MPI-2 (published in 1996). MPI-2 is, for the most part, additions and extensions to the original MPI-1 specification. The MPI-1 and MPI-2 documents can be downloaded from the official MPI Forum web site: http://www.mpi-forum.org/. Open MPI is an open source, freely available implementation of both the MPI-1 and MPI-2 documents. The Open MPI software achieves high performance the Open MPI project is quite receptive to community input.
標簽： comprising MPI Interface committee
上傳時間： 2013-12-22
上傳用戶：爺的氣質
In this paper, we describe the development of a rapidly reconfigurable system in which the users’ tacit knowledge and requirements are elicited via a process of Interactive Evolution, finding the image processing parameters to achieve the required goals without any need for specialised knowledge of the machine vision system. We show that the resulting segmentation can be quickly and easily evolved from scratch, and achieves detection rates comparable to those of a hand-tuned system on a hot-rolled steel defect recognition problem.
標簽： reconfigurable development the describe
上傳時間： 2014-01-05
上傳用戶：hopy
We introduce a sub-cell WENO reconstruction method to evaluate spatial derivatives in the high-order ADER scheme. The basic idea in our reconstruction is to use only r stencils to reconstruct the point-wise values of solutions and spatial derivatives for the 2r-1 th order ADER scheme in one dimension, while in two dimensions, the dimension-by-dimension sub-cell reconstruction approach for spatial derivatives is employed. Compared with the original ADER scheme of Toro and Titarev (2002) [2] that uses the direct derivatives of reconstructed polynomials for solutions to evaluate spatial derivatives, our method not only reduces greatly the computational costs of the ADER scheme on a given mesh, but also avoids possible numerical oscillations near discontinuities, as demonstrated by a number of one- and two-dimensional numerical tests. All these tests show that the 5th-order ADER scheme based on our sub-cell reconstruction method achieves the desired accuracy, and is essentially non-oscillatory and computationally cheaper for problems with discontinuities.
標簽： 高精度格式
上傳時間： 2016-01-13
上傳用戶：ccsdcczd
High-Speed, Low-Power Dual Operational Amplifier The AD826 features high output current drive capability of 50 mA min per amp, and is able to drive unlimited capacitive loads. With a low power supply current of 15 mA max for both amplifiers, the AD826 is a true general purpose operational amplifier. The AD826 is ideal for power sensitive applications such as video cameras and portable instrumentation. The AD826 can operate from a single +5 V supply, while still achieving 25 MHz of band width. Furthermore the AD826 is fully specified from a single +5 V to ±15 V power supplies. The AD826 excels as an ADC/DAC buffer or active filter in data acquisition systems and achieves a settling time of 70 ns to 0.01%, with a low input offset voltage of 2 mV max. The AD826 is available in small 8-lead plastic mini-DIP and SO packages.
上傳時間： 2020-04-19
上傳用戶：su1254
