this is a sensorless fan motor control code .(it use the angle-ahead commutate tech.)
標簽： angle-ahead sensorless commutate control
上傳時間： 2015-03-30
上傳用戶：aysyzxzm
Ripple Adder: 16-bit 全加,半加及ripple adder的設計及VHDL程序 Carry Look ahead Adder:4, 16, 32 bits 前置進位加法器的設計方案及VHDL程序 Carry Select Adder:16 Bits 進位選擇加法器的設計方案及VHDL程序
上傳時間： 2015-05-13
上傳用戶：我們的船長
k-step ahead predictions determined by simulation of the ％ one-step ahead neural network predictor. For NNARMAX ％ models the residuals are set to zero when calculating the ％ predictions. The predictions are compared to the observed output. ％
標簽： ahead predictions determined simulation
上傳時間： 2016-12-27
上傳用戶：busterman
verilog code 4-bit carry look-ahead adder output [3:0] s //summation output cout //carryout input [3:0] i1 //input1 input [3:0] i2 //input2 input c0 //前一級進位
標簽： output look-ahead summation carryout
上傳時間： 2017-01-07
上傳用戶：yyq123456789
verilog code 16-bit carry look-ahead adder output [15:0] sum // 相加總和 output carryout // 進位 input [15:0] A_in // 輸入A input [15:0] B_in // 輸入B input carryin // 第一級進位 C0
標簽： output look-ahead carryout verilog
上傳時間： 2014-12-06
上傳用戶：ls530720646
linux read ahead算法博士論文
上傳時間： 2017-07-25
上傳用戶：cc1
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-13
上傳用戶：瓦力瓦力hong
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-21
上傳用戶：wxqman
Grammatica is a C# and Java parser generator (compiler compiler). It improves upon simlar tools (like yacc and ANTLR) by creating well-commented and readable source code, by having automatic error recovery and detailed error messages, and by support for testing and debugging grammars without generating source code. It supports LL(k) grammars with an unlimited number of look-ahead tokens.
標簽： compiler Grammatica generator improves
上傳時間： 2015-01-11
上傳用戶：stella2015
Every day, patches are created to cover up security holes in software applications and operating systems. But by the time you download a patch, it could be too late. A hacker may have already taken advantage of the hole and wreaked havoc on your system. This innovative book will help you stay one step ahead. It gives you the tools to discover vulnerabilities in C-language-based software, exploit the vulnerabilities you find, and prevent new security holes from occurring.
標簽： applications operating security software
上傳時間： 2015-11-01
上傳用戶：fhzm5658
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