Decoding most of the infrared signals can be easily
handled by PIC16C5X microcontrollers. This application
note describes how this decoding may be done.
The only mandatory hardware for decoding IR signals
is an infrared receiver. The use of two types is
described here. Both are modular types used often by
the consumer electronics industry. The first type
responds to infrared signals modulated at about
40 kHz. The second responds to non-modulated infrared
pulses and has a restricted range. The hardware
costs of each approach will be less than two dollars.
Many applications use connection/object pool. A program may require a IMAP connection pool and LDAP connection pool. One could easily implement a IMAP connection pool, then take the existing code and implement a LDAP connection pool. The program grows, and now there is a need for a pool of threads. So just take the IMAP connection pool and convert that to a pool of threads (Copy, paste, find, replace????). Need to make some changes to the pool implementation? Not a very easy task, since the code has been duplicated in many places. Re-inventing source code is not an intelligent approach in an object oriented environment which encourages re-usability. It seems to make more sense to implement a pool that can contain any arbitrary type rather than duplicating code. How does one do that? The answer is to use type parameterization, more commonly referred to as templates.
Introducing a new product requires the designer to think about the product differentiators. Designing a user-friendly product, considering all other features are equivalent, will help increase the product acceptance and sales. A good User Interface is definitively one of these differentiators. In many instances, a Graphical User Interface (GUI) is the best approach.
關于FPGA流水線設計的論文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.
The cable compensation system is an experiment system that performs simulations of partial or microgravity environments on earth. It is a highly nonlinear and complex system.In this paper, a network based on the theory of the Fuzzy Cerebellum Model Articulation Controller(FCMAC) is proposed to control this cable compensation system. In FCMAC ,without appropriate learning rate, the control system based on FCMAC will become unstable or its convergence speed will become slow.In order to guarantee the convergence of tracking error, we present a new kind of optimization based on adaptive GA for selecting learning rate.Furthermore, this approach is evaluated and its performance is discussed.The simulation results shows that performance of the FCMAC based the proposed method is stable and more effective.
This Document provides the High Level Design specification for the Bootloader development and library porting for ADSP-BF533 based EZ-Kit Lite Board and STAMP Board. This document is meant to be the one of the inputs for the System Test Plan and the overall implementation of the same. This document also details the approach and assumptions made for the design
Verilog HDL: Magnitude
For a vector (a,b), the magnitude representation is the following:
A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm.
http://w3eval.calcsharp.net/
W3Eval is Java applet that evaluates mathematical expressions. It uses different approach from conventional calculator, which is more natural to the way people calculate.
This book is the most accurate and up-to-date source of information the STL currently available. ... It has an approach and appeal of its own: it explains techniques for building data structures and algorithms on top of the STL, and in this way appreciates the STL for what it is - a framework. Angelika Langer, Independent Consultant and C++ Report Columnist "A superbly authored treatment of the STL......an excellent book which belongs in any serious C++ developer s library." Jim Armstrong, President 2112 F/X, Texas. \n
The C++ Standard Template Library (STL) represents a breakthrough in C++ programming techniques. With it, software developers can achieve vast improvements in the reliability of their software, and increase their own productivity.
